Abstract: A transmission method executed by a transmission apparatus including a plurality of reception modules that receive packets and a plurality of transmission modules that receive the packets and transmit the packets to destinations of the packets, the transmission method includes extracting, by each of the plurality of reception modules, the amounts of data for respective priority levels of the received packets; transmitting, to one of the plurality of transmission modules, information regarding the extracted amounts of data for the respective priority levels; determining, by the one of the plurality of transmission modules, the amounts of discard data to be discarded for the plurality of respective reception modules, based on the extracted amounts of data for the respective priority levels and the amount of packet data that is able to be output; and notifying the plurality of reception modules of feedback information related to the determined amounts of discard data.

Abstract: A transmission device includes a plurality of transmitting units that transmit data to an opposing device via different paths, a determining unit that compares a first speed of an operation clock for the opposing device with a second speed of an operation clock for the transmission device, and an inserting unit that inserts, when the first speed is same as the second speed, first difference absorbing data that has a predetermined data length into the data to be transmitted by the transmitting units, that inserts, when the first speed is higher, second difference absorbing data that has a data length smaller than the predetermined data length into the data, and that inserts, when the second speed is higher, third difference absorbing data that has a data length greater than the predetermined data length into the data.

Abstract: A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.

Abstract: A data processing device connected to another data processing device through an asynchronous network to receive/transmit data from/to the other data processing device. The data processing device monitors an accumulation amount of a reception buffer for receiving data transmitted from the other data processing device, controls a self reception data processing clock based upon the monitored accumulation amount, transmits to the other data processing device transmission clock control information controlling a transmission clock in the other data processing device based upon the monitored accumulation amount, and controlling a self transmission clock based upon the clock control information transmitted from the other data processing device.

Abstract: An output-band control unit extracts delay information indicating a delay state of a packet from a packet received, and controls a setting of an output band of the packet based on the delay information. A packet-transmission control unit updates the delay information based on the output band of which the setting is controlled by the output-band control unit and an internal delay that occurs internally with respect to a packet output in the output band, and transmits the packet with the delay information updated.

Abstract: A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.

Abstract: A router includes a plurality of control units connected in parallel, each having an input connected to a receiving interface and an output connected to a transmitting interface, and performing timing control of outgoing packets to the transmitting interface based on header information of incoming packets, the incoming packets being stored in a memory and the stored packets being transmitted to the transmitting interface in order of transmission of the outgoing packets. A distributing unit distributes transmitting sequence information, related to the stored packets in the memory, to other control units. The distributing unit determines whether a packet sequence inversion in the control unit occurs, based on a result of comparison of the transmitting sequence information received and the transmitting sequence information held by the control unit, inhibiting the transmission of the stored packets to the transmitting interface when the packet sequence invention is detected.

Abstract: A router includes a plurality of control units connected in parallel, each having an input connected to a receiving interface and an output connected to a transmitting interface, and performing timing control of outgoing packets to the transmitting interface based on header information of incoming packets, the incoming packets being stored in a memory and the stored packets being transmitted to the transmitting interface in order of transmission of the outgoing packets. A distributing unit distributes transmitting sequence information, related to the stored packets in the memory, to other control units. The distributing unit determines whether a packet sequence inversion in the control unit occurs, based on a result of comparison of the transmitting sequence information received and the transmitting sequence information held by the control unit, inhibiting the transmission of the stored packets to the transmitting interface when the packet sequence invention is detected.