Patents by Inventor Hideyuki Matsumoto

Hideyuki Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130242108
    Abstract: Disclosed herein is an image transmission system including a plurality of cameras and a coaxial cable for transmitting image signals from the cameras, wherein: each of the cameras includes an imaging block configured to acquire an image signal by imaging an object, a coding block configured to compression-code the image signal through intra-frame compression and inter-frame compression so as to generate a coded signal, and a signal output block configured to output the coded signal onto the coaxial cable; and the camera of interest outputs the coded signal obtained through inter-frame compression onto the coaxial cable when another of the cameras outputs the coded signal obtained through intra-frame compression onto the coaxial cable.
    Type: Application
    Filed: February 21, 2013
    Publication date: September 19, 2013
    Applicant: SONY CORPORATION
    Inventors: Hideyuki MATSUMOTO, Tamotsu Ikeda, Tetsuya Narita
  • Publication number: 20130235194
    Abstract: Disclosed herein is an imaging apparatus including: an imaging portion capturing an image of a subject, thereby acquiring a video signal; a first coding portion compression-coding the video signal through intra-frame compression and inter-frame compression, thereby generating a first coded signal; a second coding portion compression-coding the video signal through the intra-frame compression, thereby generating a second coded signal an amount of information on which is less than that of the first coded signal; and a signal sending portion sending the first coded signal and the second coded signal to a coaxial cable.
    Type: Application
    Filed: February 13, 2013
    Publication date: September 12, 2013
    Applicant: Sony Corporation
    Inventors: Hideyuki MATSUMOTO, Tamotsu IKEDA
  • Patent number: 8484528
    Abstract: Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: July 9, 2013
    Assignee: Sony Corporation
    Inventors: Naomichi Kishimoto, Hideyuki Matsumoto, Toshiyuki Miyauchi, Yuichi Mizutani
  • Patent number: 8464124
    Abstract: A receiving apparatus receives a low density parity check (“LCPC”) code and decode the LCPC code to provide for error check capabilities. A bit error rate (“BER”) controlling section is the frequency of the LCPC by using an index comprised of BER conditional information that indicates communication conditions affecting the power consumption at the time of decoding. The frequency is controlled on the basis of a reception interval of the low density parity check code.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: June 11, 2013
    Assignee: Sony Corporation
    Inventors: Naomichi Kishimoto, Hideyuki Matsumoto, Toshiyuki Miyauchi, Yuichi Mizutani
  • Patent number: 8396434
    Abstract: Disclosed herein is a signal processing device including an adjustment section configured to adjust the power of each of subinterval signals by multiplying the subinterval signals by a gain adapted to bring the power to a given level, the subinterval signals being input signals each having a frequency component of one of a plurality of subintervals into which the frequency band over which the power spectrum is to be measured is divided, and a correction section configured to correct the power of each of the subinterval signals, whose power has been adjusted by the adjustment section, by multiplying the power spectrum by the reciprocal of the gain used for adjustment of the power by the adjustment section.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: March 12, 2013
    Assignee: Sony Corporation
    Inventors: Hiroyuki Kamata, Yuichi Hirayama, Hideyuki Matsumoto
  • Patent number: 8391681
    Abstract: A picture start code detecting section 131 detects the input timing of the leading data of a picture from TS packets inputted to a buffer 11. A counter 132 outputs a timing signal at the time when the leading data of the picture has been inputted 30 times, thereby detecting the input timing of data of one second. A counter 133 counts the data amount of TS packets inputted to the buffer 11 during the period of time from the reception of a timing signal from the counter 132 to the next reception. The count value is read via a DFF 134 and inputted to a read control section 135. The read control section 135 sets the input value from the DFF 134 as the reading speed of TS packets from the buffer 11.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: March 5, 2013
    Assignee: Sony Corporation
    Inventor: Hideyuki Matsumoto
  • Patent number: 8385371
    Abstract: A frame synchronizer, frame synchronization method and demodulator which can more positively establish frame synchronization of an input signal which is likely to have a plurality of frame lengths. A differential correlation detector calculates a differential correlation value with no pilot which is associated with the absence of a pilot signal inserted in the input signal and a differential correlation value with a pilot which is associated with the presence of a pilot signal inserted in the input signal. Frame period confirmation counters perform, based on the differential correlation values with no pilot, frame synchronization control appropriate to the input signals whose frame lengths are 21690 and 32490 symbols, respectively. The frame period confirmation counters 1 perform, based on the differential correlation values with a pilot, frame synchronization control appropriate to the input signals whose frame lengths are 22194 and 33282 symbols, respectively.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: February 26, 2013
    Assignee: Sony Corporation
    Inventors: Hideyuki Matsumoto, Tetsuhiro Futami, Atsushi Makita, Takashi Yokokawa, Doan Tien Dung, Yuichi Mizutani
  • Patent number: 8357933
    Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: January 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Hideyuki Matsumoto, Shingo Yorisaki, Yasuhiro Motoyama, Masayoshi Okamoto, Yasunori Narizuka, Naoki Okamoto
  • Patent number: 8340230
    Abstract: A receiving device includes: a noise detecting means for detecting a noise, which is contained in a received signal, using the received signal which has undergone clock synchronization processing: a phase error detecting means for detecting a phase error of the received signal using the received signal which has undergone clock synchronization processing; and a calculation means for calculating a phase correction value on the basis of the phase error detected by the phase error detecting means, wherein, when the noise is detected by the noise detecting means, the calculation means modifies a parameter to be employed in the calculation of the phase correction value so as to decrease the phase correction value.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: December 25, 2012
    Assignee: Sony Corporation
    Inventors: Yuichi Hirayama, Yoshifumi Aoki, Atsushi Makita, Hideyuki Matsumoto
  • Patent number: 8329282
    Abstract: A power transmission belt having a body made at least in part from ethylene-?-olefin rubber. At least one load carrying member is embedded in the ethylene-?-olefin rubber. First, second and third films are formed on the load carrying member. The first film is made from at least one of an isocyanate compound and an epoxy compound, the second film from polybutadiene rubber, and the third film from an ethylene-propylene-diene terpolymer.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: December 11, 2012
    Assignee: Mitsuboshi Belting Ltd.
    Inventors: Yosuke Sueto, Hideyuki Matsumoto
  • Patent number: 8227971
    Abstract: An ultra-high-pressure mercury lamp according to various embodiments is an ultra-high-pressure mercury lamp in which a luminous tube employing a quartz bulb is attached to a neck part of a reflector by injecting first cement, and a metal base is attached to the neck-part end of the luminous tube by injecting second cement, wherein, if a is the outer diameter of the first cement and second cement after injection, b is the total axial depth of the first cement and second cement after injection, and c is the outer diameter of the quartz bulb in the vicinity of the luminous tube where the metal base is attached, the following relationships are satisfied: 1.3<a/c<2.4; 0.5<b/c<1.6.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: July 24, 2012
    Assignee: Osram AG
    Inventors: Hidehiro Kohno, Hideyuki Matsumoto
  • Publication number: 20120159108
    Abstract: [PROBLEM TO BE SOLVED] To provide a control device of vending machine that can reduce rewriting time of a control program and can perform control process during the rewriting of the control program. [SOLUTION] The device of vending machine comprises an electrically rewritable nonvolatile flash memory (340) for storing an initial processing program (341) and a control program (342), and a volatile SDRAM (330). The initial processing program (341) transfers the control program (342) from the flash memory (340) to the SDRAM (330), and a control process of the vending machine is performed via execution of the control program (342) in the SDRAM (330). The writing process to the flash memory (340) is executed in parallel with the control process.
    Type: Application
    Filed: September 3, 2010
    Publication date: June 21, 2012
    Applicant: SANDEN CORPORATION
    Inventors: Takayuki Akuzawa, Hiroshi Kudose, Hideyuki Matsumoto
  • Patent number: 8203268
    Abstract: A discharge lamp configured to suppress temperature increases in the electrode on the opening part side of a reflective mirror is described. The discharge lamp includes an F electrode and an R electrode having shapes before forming the melt electrodes that satisfy at least one of the following conditions (a) to (c): (a) The diameter of the core wire of the F electrode is d1f, and the diameter of the core wire of the R electrode is d1r, then d1f>1.2×d1r; (b) The wire diameter of the coil of said F electrode is d2f, and the wire diameter of the coil of the R electrode is d2r, then d2f>1.2×d2r; (c) the number of windings of the coil of the F electrode is nf, and the number of windings of the coil of the R electrode is nr, then nf>1.2×nr.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: June 19, 2012
    Assignee: Osram AG
    Inventors: Hideyuki Matsumoto, Takashi Noguchi
  • Publication number: 20120131422
    Abstract: A transmitting device includes a setting unit that sets the data length of an error correcting code whose data length is variable, an error correcting code calculator that calculates the error correcting code having the data length set by the setting unit for transmission-subject data as an information word, and a transmitting unit that transmits, to a receiving device existing in the same device, coded data that is data of a codeword obtained by adding the error correcting code obtained by calculation by the error correcting code calculator to the transmission-subject data.
    Type: Application
    Filed: September 28, 2011
    Publication date: May 24, 2012
    Applicant: Sony Corporation
    Inventors: Tatsuo SHINBASHI, Kazuhisa Funamoto, Hideyuki Matsumoto, Hiroshi Shiroshita, Kenichi Maruko, Tatsuya Sugioka, Naohiro Koshisaka, Shigetoshi Sasaki, Masato Tamori
  • Publication number: 20120131412
    Abstract: Disclosed herein is a transmission apparatus, including: an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word; a division section adapted to allocate coded data which configure a codeword obtained by adding the error correction code determined by the calculation by the error correction code calculation section to the data of the transmission object for each predetermined number of units to a plurality of transmission lines; and a plurality of transmission sections provided corresponding to the plural transmission lines and adapted to transmit the coded data allocated by the division section to a reception apparatus through the transmission lines.
    Type: Application
    Filed: October 5, 2011
    Publication date: May 24, 2012
    Applicant: Sony Corporation
    Inventors: Tatsuo SHINBASHI, Kazuhisa Funamoto, Hideyuki Matsumoto, Hiroshi Shiroshita, Kenichi Maruko, Tatsuya Sugioka, Naohiro Koshisaka
  • Publication number: 20120124455
    Abstract: Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.
    Type: Application
    Filed: October 20, 2011
    Publication date: May 17, 2012
    Applicant: SONY CORPORATION
    Inventors: Naohiro Koshisaka, Tatsuo Shinbashi, Kazuhisa Funamoto, Hideyuki Matsumoto, Hiroshi Shiroshita, Kenichi Maruko, Tatsuya Sugioka
  • Publication number: 20120120289
    Abstract: An image outputting apparatus includes a header production section for producing a header including header information formed from first and second frame information regarding whether pixel data included in a payload are of first and last lines of one frame, respectively, first line information regarding whether or not the pixel data included in the payload are valid, and second line information regarding a line number of a line formed from the pixel data included in the payload, and an error detection code for use for detection of an error of the header information. A packet production section produces a packet which includes, in the payload thereof, pixel data for one line which configure an image obtained by imaging by an imaging section and to which the header is added. An outputting section outputs the produced packet to an image processing apparatus.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 17, 2012
    Applicant: Sony Corporation
    Inventors: Tatsuya SUGIOKA, Hiroshi Shiroshita, Miho Ozawa, Hiroki Kihara, Kenichi Maruko, Tatsuo Shinbashi, Kazuhisa Funamoto, Hideyuki Matsumoto, Takayuki Toyama, Hayato Wakabayashi, Naohiro Koshisaka, Shigetoshi Sasaki, Masato Tamori
  • Publication number: 20120120287
    Abstract: The present disclosure provides an image outputting apparatus, including, an image pickup section, an error correction code calculation section adapted to calculate an error correction code using pixel data, which configure an image obtained by image pickup by the image pickup section, as an information word, and an outputting section adapted to output coded data, which are data of a codeword obtained by adding the error correction code to the pixel data, to an image processing apparatus provided in an apparatus in which the image outputting apparatus is provided.
    Type: Application
    Filed: October 20, 2011
    Publication date: May 17, 2012
    Applicant: Sony Corporation
    Inventors: Kazuhisa FUNAMOTO, Tatsuo Shinbashi, Hideyuki Matsumoto, Hiroshi Shiroshita, Hiroki Kihara, Kenichi Maruko, Tatsuya Sugioka, Naohiro Koshisaka, Shigetoshi Sasaki, Masato Tamori, Takayuki Toyama, Miho Ozawa, Hayato Wakabayashi
  • Publication number: 20120110284
    Abstract: The present invention relates to a data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus. A read/write control portion 73 executes read/write control in which slots subject to extraction of two or more slots in one frame that is a collection of two or more slots each of which is a unit of error correction coding are written to a ring buffer 71 and the slots subject to extraction in one frame written to the ring buffer 71 are read within the unit time. When slots subject to extraction are changed, an output portion 76 executes output processing in which dummy data outputted from a dummy data output portion 75 are outputted with a timing immediately before a change start frame that is a frame from which the change of slots subject to extraction is started and, slots subject to extraction read from the ring buffer 71 are outputted for frames subsequent to the change start frame.
    Type: Application
    Filed: June 23, 2010
    Publication date: May 3, 2012
    Applicant: Sony Corporation
    Inventors: Hideyuki Matsumoto, Yuichi Mizutani
  • Patent number: 8170170
    Abstract: Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by the frequency synchronizing means and supplying the residual frequency error to the frequency synchronizing means, and the frequency synchronizing means performs frequency pull-in for the residual frequency error supplied from the residual frequency error detecting means after first timing.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: May 1, 2012
    Assignee: Sony Corporation
    Inventors: Hideyuki Matsumoto, Tetsuhiro Futami, Koji Naniwada, Yuichi Hirayama