Patents by Inventor Hideyuki Noda

Hideyuki Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7445755
    Abstract: Provided is a convenient process of manufacturing a two-dimensional bead array on a chip by disposing a plurality of beads immobilized with a biomolecular probe in a bead array container in a predetermined order. The bead array chip is manufactured by repeating the following operations: a container having a plurality of first channels disposed in parallel with each other and a second channel crossing therewith is retained in a container retaining portion and a capillary is moved through the second channel of the container vertically. The capillary is moved downward to suck and retain, in an end thereof, one bead stored in a storing portion of a bead storing plate and then, moved upward to the position of a desired first channel. Under this state, pure water is fed to the first passage from a water feed system and a water stream is generated by sucking the pure water by a suction pump.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: November 4, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Noda, Yoshinobu Kohara
  • Publication number: 20080261294
    Abstract: An apparatus includes a system for guiding chemiluminescence and a system for preventing a variation in dark currents. The apparatus includes a first light shielding BOX having a sample container holder and a shutter unit therein, the shutter unit including a top plate which is partly formed by a movement of a plate member and a second light shielding BOX having a photodetector therein. While a measurement is not implemented, the shutter unit is closed to block entrance of stray light to the photodetector, and while a measurement is implemented, the plate member is moved to open the shutter unit and the tip of the photodetector is inserted into a through hole formed in the top plate, so that the distance between the bottom of the sample container and a sensitive area of the photodetector is reduced to several millimeters or less.
    Type: Application
    Filed: February 21, 2008
    Publication date: October 23, 2008
    Inventors: Hideyuki Noda, Satoshi Ozawa, Masahiro Okanojo, Kenko Uchida
  • Publication number: 20080241871
    Abstract: The present invention provides a luminescence measuring method that can be accurately and quickly carried out while inhibiting a possible background associated with viable bacteria adhering to a nozzle or Adenosine Tri Phosphate remaining in the nozzle, and an apparatus for the method. The present invention uses a washing apparatus characterized by including a nozzle, a lysys solution, a luminescence reagent solution, and a detection section, as well as a relevant washing method and a relevant luminescence measuring method. To remove viable bacteria adhering to the nozzle, the nozzle is immersed in the lysys solution and then in the luminescence reagent solution. The detection section monitors luminescence occurring during a washing process.
    Type: Application
    Filed: January 25, 2008
    Publication date: October 2, 2008
    Inventors: Masahiro Okanojo, Satoshi Ozawa, Hideyuki Noda, Masaaki Hirano
  • Patent number: 7358098
    Abstract: Beads having diameters of several tens of micrometers to several millimeters and immobilized with biomolecules are captured by one kind of bead capturing nozzle one by one without fail. Using a bead holding plate having a plurality of wells each of which holds a plurality of the beads and a solution, a vibration generator mounted with a stage to attach the bead holding plate, and a bead capturing nozzle for bead capture connected to a suction pump, only a single bead is captured at the tip of the bead capturing nozzle by inserting the nozzle having an inner diameter smaller than the beads and a negative pressure inside created by the pump into the solution to allow the nozzle to come in contact with the beads in the well, applying a vibration to the bead holding plate by the vibration generator, and withdrawing the bead capturing nozzle into the air.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: April 15, 2008
    Assignee: Hitachi Software Engineering Co., Ltd.
    Inventors: Hideyuki Noda, Yoshinobu Kohara
  • Publication number: 20070245168
    Abstract: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.
    Type: Application
    Filed: May 9, 2007
    Publication date: October 18, 2007
    Inventors: Hideyuki Noda, Katsumi Dosaka
  • Patent number: 7277306
    Abstract: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: October 2, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hideyuki Noda, Katsumi Dosaka
  • Publication number: 20070207064
    Abstract: The invention provides a method in which an annular or spiral droplet holder formed of wire is used to hold a droplet in a state of being hung therefrom or being contained therein. A means for moving the droplet holder is added to the droplet holder to enable droplet transfer. To merge two droplets, they are brought into contact. To drip the droplet held by a droplet holder formed of wire, the droplet holder is deformed using an external force. A light path which passes through a droplet is set to enable optical measurement. The present invention enables inexpensive, simple droplet transfer. An inexpensive, simple configuration for handling droplets in the fields of chemical analysis, biochemical analysis, and automatic blood analysis can be realized according to the present invention.
    Type: Application
    Filed: February 16, 2007
    Publication date: September 6, 2007
    Inventors: Yoshinobu Kohara, Masataka Shirai, Hideyuki Noda, Tomoyuki Sakai, Kenko Uchida
  • Publication number: 20070180006
    Abstract: In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.
    Type: Application
    Filed: January 26, 2007
    Publication date: August 2, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Takayuki Gyoten, Katsumi Dosaka, Hideyuki Noda, Tetsushi Tanizaki
  • Publication number: 20070058407
    Abstract: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 15, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito, Hideyuki Noda
  • Patent number: 7182916
    Abstract: There are provided a novel method and technology for arraying micro-particles. Micro-particle trapping capillaries each having an inner diameter smaller than the outer diameter of probe-immobilized micro-particles are prepared. By vacuuming the inside of each micro-particle trapping capillary, only one of the micro-particles is vacuumed onto an opening at the tip thereof and taken out from holders holding a plurality of the micro-particles. The micro-particle vacuumed onto the opening at the tip of each micro-particle trapping capillary is positioned at the opening of the capillary or the edge of each channel provided in a chip, the channels each having an inlet and an outlet with a slightly larger width than the outer diameter of the micro-particle so as to allow passage of only one micro-particle. The micro-particle vacuumed onto the opening at the capillary tip is injected into the capillary from the opening of the capillary or the channel edge of the chip.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: February 27, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Noda, Yoshinobu Kohara, Kazunori Okano
  • Patent number: 7157773
    Abstract: A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: January 2, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kato, Shigehiro Kuge, Hideyuki Noda, Fukashi Morishita, Shuichi Ueno
  • Publication number: 20060257994
    Abstract: Beads having diameters of several tens of micrometers to several millimeters and immobilized with biomolecules are captured by one kind of bead capturing nozzle one by one without fail. Using a bead holding plate having a plurality of wells each of which holds a plurality of the beads and a solution, a vibration generator mounted with a stage to attach the bead holding plate, and a bead capturing nozzle for bead capture connected to a suction pump, only a single bead is captured at the tip of the bead capturing nozzle by inserting the nozzle having an inner diameter smaller than the beads and a negative pressure inside created by the pump into the solution to allow the nozzle to come in contact with the beads in the well, applying a vibration to the bead holding plate by the vibration generator, and withdrawing the bead capturing nozzle into the air.
    Type: Application
    Filed: August 3, 2005
    Publication date: November 16, 2006
    Inventors: Hideyuki Noda, Yoshinobu Kohara
  • Patent number: 7102954
    Abstract: In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: September 5, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Takeshi Fujino
  • Publication number: 20060143428
    Abstract: An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into a data train of word parallel and bit serial data. Data transfer efficiency in a signal processing device performing parallel operational processing can be increased without impairing parallelism of the processing.
    Type: Application
    Filed: November 21, 2005
    Publication date: June 29, 2006
    Inventors: Hideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Kazunori Saito
  • Publication number: 20060083667
    Abstract: There will be provided a chemical reaction device and a chemical reaction apparatus capable of performing transverse liquid movement in a simple structure and at low cost without causing contamination and air bubbles. There will be installed a mechanism for supporting the chemical reaction device in any other position than a center of a turntable which can be rotated, for moving liquid by a centrifugal force due to rotation, and for reversing a direction of the flow path independently of the turntable.
    Type: Application
    Filed: January 28, 2005
    Publication date: April 20, 2006
    Inventors: Yoshinobu Kohara, Hideyuki Noda
  • Publication number: 20060039173
    Abstract: The present invention provides a content addressable memory (CAM) with no problem in operation speed reduction and with small power consumption on an SOI substrate. The CAM includes a data memory part DM and a data comparison part DC which compares data provided on a search line SL with data stored in the data memory part DM. In the case of a mismatch, a match line ML precharged to H level is discharged to be L level. Here, gates and bodies of respective NMOS transistors N6 and N8, which constitute data comparison part DC, are short-circuited to lower threshold voltages of NMOS transistors N6 and N8. Therefore, even if lowering of voltage of search line SL connected to gate is performed, turn-on current of MOS transistors N6 and N8 can be increased to discharge the match line ML with high speed. As a result, even if lowering of power consumption of the search line SL is performed to lower power consumption, a CAM with no problem in operation speed reduction can be realized.
    Type: Application
    Filed: August 23, 2005
    Publication date: February 23, 2006
    Inventor: Hideyuki Noda
  • Publication number: 20050287549
    Abstract: This invention provides a method of genetic testing that enables testing of a plurality of variation sites (SNPs) in a cost-effective and simple manner, allowing realization of genetic diagnosis in clinical settings. The SNP type of the nucleic acid sample is evaluated by: allowing a nucleic acid sample having an anchor sequence at its 5? end to hybridize to a support having, immobilized on its surface, a probe containing a sequence that is complementary to the target sequence (the SNP region); extending a complementary strand from the probe utilizing the nucleic acid sample as a template; dissociating and removing the nucleic acid sample from the extended probe; extending a complementary strand using the extended probe as a template and a primer having a sequence identical to the anchor sequence; and detecting pyrophosphoric acid generated via the primer extension, based on bioluminescence.
    Type: Application
    Filed: January 25, 2005
    Publication date: December 29, 2005
    Inventors: Keiichi Nagai, Kazunori Okano, Hideyuki Noda, Hiroko Matsunaga, Kiyomi Taniguchi, Yoshiaki Yazawa, Tomoharu Kajiyama
  • Publication number: 20050289407
    Abstract: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 29, 2005
    Applicant: Renesas Technology Corporation
    Inventors: Hideyuki Noda, Katsumi Dosaka
  • Publication number: 20050285862
    Abstract: A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 29, 2005
    Inventors: Hideyuki Noda, Kazunori Saitoh, Kazutami Ariomoto, Katsumi Dosaka
  • Patent number: 6930950
    Abstract: An XOR gate receives an input from a pair of read data lines to output a self-precharge signal when there is an increased potential difference between the paired read data lines. Thus, immediately after the increased potential difference between the paired read data lines occurs upon issuance of a read command, a precharge operation is autonomically performed. Therefore, no external precharge command is necessary when the read command is issued and thus a higher-speed operation is easily achieved.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: August 16, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Mitsuya Kinoshita, Hideyuki Noda