Abstract: An image magnifying circuit is made up of a frame memory 12 for storing input image data, a coefficient memory 18 in which filter coefficients corresponding to a plurality of magnification ratios are stored, a non-linear magnification controller 20 for outputting an enable signal for reading the corresponding image data from the frame memory 12 and a coefficient selecting address AD3 for reading the corresponding filter coefficient from the coefficient memory 18, on the basis of an area width w predetermined to divide a display screen into n parts and a predetermined magnification for the n parts, and a filter 14 for filtering the image data from the frame memory 12 on the basis of the filter coefficients from the coefficient memory 18 to output the image data on the image which is non-linearly magnified in a horizontal direction. These filter coefficients correspond to the magnification ratio which are set for the n parts of the display screen.

Abstract: An image processor containing an EPROM (38) stored with coefficient data for image enlargement and reduction, coefficient read controllers (40-44) for reading out coefficient data from the EPROM (38) according to an enlargement/reduction selection signal, a variable horizontal characteristic filter (16) for executing either image enlargement or image reduction according to the coefficient data, a variable vertical characteristic filter (18) also for executing either image enlargement or image reduction according to the coefficient data, a frame memory (20), a contour correcting circuit (14), and selectors (22-30). When image enlargement is selected by selectors (22-30), input video signals are processed by the contour correcting circuit (14), the frame memory (20), and the filters (16,18) in this order while, when image reduction is selected, input video signals are processed by the same in the reverse order.