Abstract: A reflection-type terahertz spectrometer includes an input optical path through which terahertz waves are propagated, an irradiating mechanism that irradiates a sample with terahertz waves propagated through the input optical path, an output optical path through which terahertz waves exiting from the irradiating mechanism are propagated, and a detector that receives and detects the terahertz waves propagated through the output optical path. The irradiating mechanism has at least one planar interface and a refractive index greater than that of a peripheral region contacting the planar interface and is disposed between the input optical path and the output optical path such that the terahertz waves propagated through the input optical path to be incident on the planar interface undergo total internal reflection at the planar interface, and the sample is disposed in the peripheral region contacting the planar interface of the irradiating mechanism.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: A fiber laser system is provided with a laser cavity including at least a gain fiber, an output coupling mirror, and a saturable absorber mirror. A photo sensor detects leakage light passing through the saturable absorber mirror, for purposes of monitoring the performance of the laser system. The saturable absorber mirror may include a semiconductor saturable absorber having a Bragg reflector monolithically formed on one side thereof.

Abstract: A terahertz wave-generating semiconductor crystal includes a zincblende-type III-V compound semiconductor crystal that generates terahertz wave pulses upon application of an ultrashort light pulse in the optical communication band serving as a pump beam.

Abstract: A multi-channeled measuring method for measuring a spectrum of a terahertz pulse includes the steps of a terahertz pulse generating step for generating a terahertz pulse by using an ultrashort pulsed pumping light, a white light generating step for generating a white light pulse by using an ultrashort pulsed probe light, a stretching step for stretching and chirping the white light pulse generated at the white light pulse generating step, an electro-optic modulating step for modulating the chirped white light pulse stretched and chirped at the stretching step in such a manner that the terahertz pulse and the chirped white light pulse irradiate into an electro-optic crystal synchronously, so that the chirped white light pulse is modulated by an electric field signal induced at the electro-optic crystal irradiated by the terahertz pulse, a multi-channeled spectral detecting step for detecting a spectrum of chirped white light pulse modulated at the electro-optic modulating step by a multi-channeled detector, an

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: A fault verification apparatus performs a logic simulation of a circuit having a normal delay and a logic simulation of a circuit in which delay is intentionally changed for a node and compares the simulation results at a specific time and checks whether or not a test pattern can detect a fault due to a delay abnormality. The apparatus performs the logic simulation by applying the test pattern to the normal circuit and a variety of fault types and compares the expected values obtained from the results of the respective logic simulations and verifies whether or not the test pattern can detect the delay fault by whether or not the expected values are different from each other at a specific comparison point.