Abstract: In a method of supporting a layout design, a net list of an integrated circuit is divided into net lists of clock domain circuit aggregations. A timing constraint is generated to each of the clock domain circuit aggregations. An arrangement order of the clock domain circuit aggregations is determined to satisfy the timing constraint. A layout of the integrated circuit is generated by carrying out arrangement and wiring of the clock domain circuit aggregations based on the arrangement order.

Abstract: A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.

Abstract: In a method of supporting a layout design, a net list of an integrated circuit is divided into net lists of clock domain circuit aggregations. A timing constraint is generated to each of the clock domain circuit aggregations. An arrangement order of the clock domain circuit aggregations is determined to satisfy the timing constraint. A layout of the integrated circuit is generated by carrying out arrangement and wiring of the clock domain circuit aggregations based on the arrangement order.

Abstract: A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.

Abstract: A modulation circuit is provided that generates an output signal obtained by modulating an input signal with a local signal and includes a local input section that receives the local signal and generates the local signal and an inverted local signal obtained by inverting the local signal, a signal input section that receives the input signal and generates the input signal and an inverted input signal obtained by inverting the input signal, a first multiplying section that outputs from a terminal that receives the input signal a first multiplied signal obtained by multiplying the local signal with the input signal, a second multiplying section that outputs from a terminal that receives the inverted input signal a second multiplied signal obtained by multiplying the inverted local signal with the inverted input signal, an output section that adds the first multiplied signal to the second multiplied signal and generates the output signal, and a transmission line that sends to the output section the first multipl

Abstract: A balun circuit is provided that includes a first coupling line in which an unbalanced line thereof is connected to a first terminal and a balanced line thereof is electrically connected to a second terminal, a second coupling line in which an unbalanced line thereof is electrically connected to the unbalanced line of the first coupling line and a balanced line thereof is electrically connected to a third terminal, a first transmission path that is serially connected between the balanced line of the first coupling line and a ground potential, a second transmission path that is serially connected between the balanced line of the second coupling line and a ground potential, and a third transmission path that is serially connected between the unbalanced line of the first coupling line and the unbalanced line of the second coupling line.

Abstract: A modulation circuit is provided that generates an output signal obtained by modulating an input signal with a local signal and includes a local input section that receives the local signal and generates the local signal and an inverted local signal obtained by inverting the local signal, a signal input section that receives the input signal and generates the input signal and an inverted input signal obtained by inverting the input signal, a first multiplying section that outputs from a terminal that receives the input signal a first multiplied signal obtained by multiplying the local signal with the input signal, a second multiplying section that outputs from a terminal that receives the inverted input signal a second multiplied signal obtained by multiplying the inverted local signal with the inverted input signal, an output section that adds the first multiplied signal to the second multiplied signal and generates the output signal, and a transmission line that sends to the output section the first multipl

Abstract: A balun circuit is provided that includes a first coupling line in which an unbalanced line thereof is connected to a first terminal and a balanced line thereof is electrically connected to a second terminal, a second coupling line in which an unbalanced line thereof is electrically connected to the unbalanced line of the first coupling line and a balanced line thereof is electrically connected to a third terminal, a first transmission path that is serially connected between the balanced line of the first coupling line and a ground potential, a second transmission path that is serially connected between the balanced line of the second coupling line and a ground potential, and a third transmission path that is serially connected between the unbalanced line of the first coupling line and the unbalanced line of the second coupling line.

Abstract: A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing circuit blocks based on a netlist. The step (b) is the step of estimating an interconnection length between two of the placed circuit blocks based on the netlist and positions of the placed circuit blocks. The step (c) is the step of judging whether the estimated interconnection length satisfies timing constraints for connections among the circuit blocks, based on relation data indicating relations among interconnection lengths and timings. The step (d) is the step of outputting the judgment result.

Abstract: The frequency characteristic of a conversion loss is kept generally constant during conversion of a high frequency received signal into an intermediate frequency signal. There is provided a frequency converter including a balanced balun (10) which branches a locally oscillated signal (Lo) into two signals which have the same amplitude and are different from each other in phase by 180 degrees, low-pass filters (12a, 12b) through which the two signals pass, and antiparallel diode pairs (16a, 16b) which respectively mix outputs from the low-pass filters (12a, 12b) with a high frequency received signal (RF) to produce an intermediate frequency signal (IF) The low-pass filters (12a, 12b) exhibit generally constant impedances in the frequency band of the high frequency received signal (RF).

Abstract: A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing circuit blocks based on a netlist. The step (b) is the step of estimating an interconnection length between two of the placed circuit blocks based on the netlist and positions of the placed circuit blocks. The step (c) is the step of judging whether the estimated interconnection length satisfies timing constraints for connections among the circuit blocks, based on relation data indicating relations among interconnection lengths and timings. The step (d) is the step of outputting the judgment result.

Abstract: A verification method of an integrated circuit including an input/output buffer placed in a periphery of a semiconductor device and an internal circuit. The verification method stores physical information on routing of the input/output buffer into a library of the input/output buffer and verifies a placement of the input/output buffer based on the physical information.

Abstract: An automatic arrangement and wiring apparatus (10) for a semiconductor integrated circuit that can remove or reduce variations in wiring areas (channels) for a top hierarchy is disclosed.