Abstract: An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively.

Abstract: An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively.

Abstract: An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively.

Abstract: An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively.

Abstract: In the semiconductor integrated circuit device of the present invention which uses MOSFETs as its components, the gate electrode of the MOSFET is constructed by using a silicide gate, a polycide gate or a metal gate. The source-drain region of the MOSFET for the internal circuit which does not require connection to an external circuit has a silicide structure, and the source-drain region of the MOSFET for the buffer circuit which requires a direct connection to an external device has a region which is not of silicide structure at least in a portion adjacent to the gate electrode. The gate electrode and the source-drain region of the internal circuit have low resistances so that it is possible to realize an increase in the operating speed by using them as a part of the wirings. Further, in the source-drain region of the buffer circuit there is provided a region of high resistance in the vicinity of the gate electrode so that it is possible to enhance the ESD resistance.

Abstract: Formation of an integrated circuit device with the trench isolation process is disclosed. A plurality of circuit elements such as transistors are isolated from one another by trenches formed in field isolation regions of a semiconductor substrate. Each trench should be filled with appropriate materials to maintain the flatness of the surface of the substrate. Borophosphosilicate glass (BPSG) is employed as the material filled into each trench.

Abstract: A method of manufacturing an insulated gate field effect transistor has first and second impurity doping processes for forming source and drain regions. In the first doping process, an impurity is lightly doped in the source and drain forming regions in self-alignment with a silicon gate pattern and a field insulating film. Next, a heat treatment is conducted so that the side surface portions of the silicon gate pattern are converted into silicon oxide films having a predetermined thickness. Thereafter, the second doping process is conducted in which an impurity is heavily doped in each part of the source and drain forming region in self-alignment with the silicon oxide films and the field insulating film. Each of source and drain region manufactured by the method has a first part of low impurity concentration adjacent to a channel region and a second part of high impurity concentration positioned between the first part and the field insulating film.