Patents by Inventor Hideyuki Oshima
Hideyuki Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11275104Abstract: A waveform data acquisition module acquires the waveforms of electrical signals for multiple channels. A memory controller continuously writes a digital signal S3 to one from among a first memory unit and a second memory unit. When a given memory unit has become full, the memory controller notifies an external higher-level controller that the corresponding memory unit is full and switches the wiring target to the other memory unit.Type: GrantFiled: January 14, 2020Date of Patent: March 15, 2022Assignee: ADVANTEST CORPORATIONInventors: Takeshi Yaguchi, Kazushige Yamamoto, Hideyuki Oshima, Shintaro Ichikai
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Publication number: 20200309833Abstract: A waveform data acquisition module acquires the waveforms of electrical signals for multiple channels. A memory controller continuously writes a digital signal S3 to one from among a first memory unit and a second memory unit. When a given memory unit has become full, the memory controller notifies an external higher-level controller that the corresponding memory unit is full and switches the wiring target to the other memory unit.Type: ApplicationFiled: January 14, 2020Publication date: October 1, 2020Inventors: Takeshi YAGUCHI, Kazushige YAMAMOTO, Hideyuki OSHIMA, Shintaro ICHIKAI
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Target value search circuit, taget value search method, and semiconductor test device using the same
Patent number: 7444576Abstract: In a tentative target value calculation section 28, a predetermined value is subtracted from (or added to) a target value Exp to calculate a tentative target value ExpB. In a binary search executing section 25, binary search is executed, and a searching region is limited to a certain region including this tentative target value ExpB. Next, in a sequential search executing section 29, the target value Exp is searched for in an increasing direction from the tentative target value ExpB which is a start point in the limited searching region. Accordingly, both drop prevention of measurement precision and reduction of searching time are achieved consistently, and a target value is securely and normally found in a case where a sequence constituting a searching object indicates an ascending-order sequence including a decrease in a part.Type: GrantFiled: October 24, 2003Date of Patent: October 28, 2008Assignee: Advantest Corp.Inventor: Hideyuki Oshima -
Patent number: 7330045Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.Type: GrantFiled: February 20, 2007Date of Patent: February 12, 2008Assignee: Advantest Corp.Inventor: Hideyuki Oshima
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Publication number: 20070146000Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.Type: ApplicationFiled: February 20, 2007Publication date: June 28, 2007Inventor: Hideyuki Oshima
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Patent number: 7196534Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.Type: GrantFiled: December 18, 2003Date of Patent: March 27, 2007Assignee: Advantest Corp.Inventor: Hideyuki Oshima
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Patent number: 7187192Abstract: A semiconductor test device for acquiring a multiplexed clock signal from LSI output data and using the clock to test the LSI. The device includes a time interpolator and registers connected in series. The time interpolator has flip-flops connected in parallel for receiving output data from an LSI under test, a delay circuit for successively inputting strobes delayed at a constant timing interval to the flip-flops and outputting time-series level data, and an encoder for receiving the time-series level data from the flip-flops and encoding it into position data indicating an edge timing. The registers successively store position data from the encoder and output them at a predetermined timing. The device further includes a digital filter for outputting the position data from the registers as a recovery clock.Type: GrantFiled: April 21, 2003Date of Patent: March 6, 2007Assignee: Advantest Corp.Inventors: Hideyuki Oshima, Yasutaka Tsuruki
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Patent number: 7078889Abstract: A recovery clock synchronized with an internal clock faster than a system clock is obtained with an edge timing of the system clock output from a DUT. The present invention includes: a time interpolator 20 which includes flip-flops (FF 21) which receive system clocks of the DUT 1, a delay circuit 22 which outputs time-series level data, from the FF 21, and an encoder 28 which receives the time-series level data output and encodes it into positional data indicative of an edge timing; a digital filter 40 which includes a plurality of registers 41 which sequentially store the positional data and output the positional data as a recovery clock; and a data side selector 30 which selects output data of the DUT 1 base on the recovery clock.Type: GrantFiled: December 26, 2003Date of Patent: July 18, 2006Assignee: Advantest Corp.Inventor: Hideyuki Oshima
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Publication number: 20060156126Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.Type: ApplicationFiled: December 18, 2003Publication date: July 13, 2006Inventor: Hideyuki Oshima
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Target value search circuit, taget value search method, and semiconductor test device using the same
Publication number: 20060020577Abstract: In a tentative target value calculation section 28, a predetermined value is subtracted from (or added to) a target value Exp to calculate a tentative target value ExpB. In a binary search executing section 25, binary search is executed, and a searching region is limited to a certain region including this tentative target value ExpB. Next, in a sequential search executing section 29, the target value Exp is searched for in an increasing direction from the tentative target value ExpB which is a start point in the limited searching region. Accordingly, both drop prevention of measurement precision and reduction of searching time are achieved consistently, and a target value is securely and normally found in a case where a sequence constituting a searching object indicates an ascending-order sequence including a decrease in a part.Type: ApplicationFiled: October 24, 2003Publication date: January 26, 2006Inventor: Hideyuki Oshima -
Patent number: 6956395Abstract: A tester comprising a reference clock generating section for generating a reference clock having a first frequency, a first test rate generating section for generating a first test rate clock having a frequency which is about an integral multiple of the first frequency, a second test rate generating section for generating a second test rate clock having a frequency which is about an integral multiple of the first frequency and different from the frequency of the first test rate clock, a first driver section for supplying a test pattern to an electronic device according to the first test rate clock, and a second deriver section for supplying the test pattern to the electronic device according to the second test rate clock.Type: GrantFiled: July 12, 2004Date of Patent: October 18, 2005Assignee: Advantest CorporationInventors: Hideyuki Oshima, Yasutaka Tsuruki
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Publication number: 20050149801Abstract: A recovery clock synchronized with an internal clock faster than a system clock is obtained with an edge timing of the system clock output from a DUT. The present invention is configured to comprise: a time interpolator 20 which includes flip-flops 21a to 21n which receive system clocks of the DUT 1, a delay circuit 22 which sequentially receives strobes delayed at specified timing intervals to the FF 21 and outputs time-series level data, and an encoder 28 which receives the time-series level data output from the FF 21 and encodes it into positional data indicative of an edge timing; a digital filter 40 which includes a plurality of registers 41a to 41n which sequentially store the positional data of the encoder 28 and output it with a predetermined timing, and outputs the positional data from the register 41 as a recovery clock; and a data side selector 30 which selects output data of the DUT 1 with the recovery clock being used as a selection signal.Type: ApplicationFiled: December 26, 2003Publication date: July 7, 2005Inventor: Hideyuki Oshima
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Publication number: 20040239310Abstract: A tester comprising a reference clock generating section for generating a reference clock having a first frequency, a first test rate generating section for generating a first test rate clock having a frequency which is about an integral multiple of the first frequency, a second test rate generating section for generating a second test rate clock having a frequency which is about an integral multiple of the first frequency and different from the frequency of the first test rate clock, a first driver section for supplying a test pattern to an electronic device according to the first test rate clock, and a second deriver section for supplying the test pattern to the electronic device according to the second test rate clock.Type: ApplicationFiled: July 12, 2004Publication date: December 2, 2004Inventors: Hideyuki Oshima, Yasutaka Tsuruki