Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector.

Abstract: An image capturing apparatus comprises an image sensor comprising an imaging pixel for receiving light through an opening with a center position coincident with the optical axis of a microlens, first and second focus detection pixels for receiving pupil-divided light through a first and second opening offset in first and second directions from the optical axis of a microlens, respectively; ROM for storing shading correction data; correction coefficient generation unit for generating shading correction coefficients respectively for the imaging pixel, and the first and second focus detection pixels from the shading correction data; and correction unit for subjecting a signal for the imaging pixel to shading correction with the use of the shading correction coefficient for the imaging pixel, and subjecting signals for the first and second focus detection pixels to shading correction with the use of the shading correction coefficients for the first and second focus detection pixels.

Abstract: A rate conversion unit determines a frame thinning-out rate to thin out frames on the basis of a recording rate at the time of photographing and a display rate for display on a display apparatus so that a temporal updating interval of a video image between continuous fields becomes constant. After that, a frame is repeatedly inserted so that a frame rate becomes equal to the display rate.

Abstract: An image capturing apparatus includes an image sensor 104 in which at least part of pixels arranged in two dimensions are configured as focus detection pixels with divided-pupil, a memory control circuit 113 configured to read out from a memory position information for the focus detection pixels 401, 402 stored in the memory, and a correction circuit 110 configured to identify positions of the focus detection pixels 401, 402 in the image sensor 104 based on the position information for the focus detection pixels 401, 402 and to correct a defective focus detection pixel signal using defect-free focus detection pixel signals.

Abstract: An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit.

Abstract: An image capture device includes a first clock generating unit that generates a first clock for sampling a video signal using a first crystal oscillator, a second clock generating unit that generates a second clock for sampling an audio signal using a second crystal oscillator, a calculating unit that calculates a correction value for adjusting a shift between the first clock and the second clock, and an adjusting unit that adjusts a driving timing of a capturing unit according to the correction value.

Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: An image capture device includes a first clock generating unit that generates a first clock for sampling a video signal using a first crystal oscillator, a second clock generating unit that generates a second clock for sampling an audio signal using a second crystal oscillator, a calculating unit that calculates a correction value for adjusting a shift between the first clock and the second clock, and an adjusting unit that adjusts a driving timing of a capturing unit according to the correction value.

Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: In an image sensing apparatus which uses a solid-state image sensing device, it is an object of the present invention to minimize smear. In order to achieve the object, a solid-state image sensing apparatus includes a solid-state image sensing device, a calculation unit which calculates a signal correction amount from an output signal from the solid-state image sensing device, an indication unit (even_odd_flag) which indicates whether the above output signal is output from an even-numbered line or odd-numbered line of the solid-state image sensing deice, the first correction unit which corrects the signal correction amount in accordance with the output from this indication unit, and the first subtraction unit which subtracts, from the above output signal, the signal correction amount corrected by the first correction unit.

Abstract: An image defect correction apparatus capable of satisfactorily correcting a white vertical line caused by point defects on the same vertical CCD. A first correction value is determined from a difference between an average value of luminance signals obtained by a vertical CCD including one or more point defects and an average value of luminance signals obtained by the vertical CCDs when light-receiving elements face a predetermined ineffective signal region. It is determined to which of regions divided by Y addresses of point defects on the same vertical CCD each of Y-directional positions of luminance signals outputted from a horizontal CCD is positioned. The first correction value is multiplied by a predetermined coefficient corresponding to the determined region to calculate a second correction value with which the luminance signals from the horizontal CCD are corrected.

Abstract: An image processing apparatus includes a determining unit that determines whether image capturing conditions concerning super-resolution processing are satisfied for each piece of image data, and an adding unit that adds data corresponding to a result of determination made by the determining unit to each piece of the image data.

Abstract: A resister configuration control device which is capable of updating resister configuration values during a non-display period without increasing a circuit scale. A FIFO selector 103 receives register configuration value information comprising a register configuration value and address information, and selects a transmission destination to which the register configuration value information is to be sent, from FIFOs 108 and 109 based on the address information and sends the register configuration value information to the selected destination. The FIFO 108 or 109 temporarily stores the register configuration value information sent from the FIFO selector 103, and reads-out and outputs the register configuration value information in predetermined timing.

Abstract: A rate conversion unit determines a frame thinning-out rate to thin out frames on the basis of a recording rate at the time of photographing and a display rate for display on a display apparatus so that a temporal updating interval of a video image between continuous fields becomes constant. After that, a frame is repeatedly inserted so that a frame rate becomes equal to the display rate.

Abstract: An image signal processing apparatus which is capable of preventing the “simultaneous display of an original image and the immediately preceding image” as well as dropping of frames. A signal processor subjects an image pickup signal corresponding to a subject outputted from an image pickup device to signal processing. A VRAM (Video Random Access Memory) section is composed of at least three storage areas that store image signals outputted from the signal processing circuit. A VRAM management information section stores management information indicative of storage states of the respective storage areas of the VRAM section. A compression circuit subjects an image signal read from the VRAM section to compression processing. An image display processing circuit subjects an image signal read from the VRAM section to image display processing. An image display section displays images based on the image signal outputted from the image display processing circuit.

Abstract: An image capture device includes a first clock generating unit that generates a first clock for sampling a video signal using a first crystal oscillator, a second clock generating unit that generates a second clock for sampling an audio signal using a second crystal oscillator, a calculating unit that calculates a correction value for adjusting a shift between the first clock and the second clock, and an adjusting unit that adjusts a driving timing of a capturing unit according to the correction value.

Abstract: In an image sensing apparatus which uses a solid-state image sensing device, it is an object of the present invention to minimize smear. In order to achieve the object, a solid-state image sensing apparatus includes a solid-state image sensing device, a calculation unit which calculates a signal correction amount from an output signal from the solid-state image sensing device, an indication unit (even_odd_flag) which indicates whether the above output signal is output from an even-numbered line or odd-numbered line of the solid-state image sensing deice, the first correction unit which corrects the signal correction amount in accordance with the output from this indication unit, and the first subtraction unit which subtracts, from the above output signal, the signal correction amount corrected by the first correction unit.

Abstract: An image processing apparatus and method capable of decoding and varying at high speed encoded image data having an arbitrary image size by using a memory of a small capacity, and a recording medium storing programs executing such a method are provided. In the image processing apparatus and method, image data encoded in each of block units is decoded in the block unit basis. In order to convert the decoded block scan sequential image data into raster scan sequential image data, the decoded image data is divided in the horizontal direction and converted, and the divided and converted data is varied.