Patents by Inventor Hideyuki Sameshima

Hideyuki Sameshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8389406
    Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: March 5, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Hideyuki Sameshima, Tomoo Ono
  • Publication number: 20110315555
    Abstract: Disclosed is a plating method including: performing plating on a plating surface of a plating substrate with a cathode electrode contacting an area in an outer circumferential section of the plating substrate where the cathode electrode is to be contacted, the plating substrate being provided with a dummy plating area between the area where the cathode electrode is to be contacted and a product area on the plating surface of the plating substrate, by supplying a plating solution to the plating surface of the plating substrate and applying electric current between the cathode electrode and an anode electrode via the plating solution.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 29, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Hirokazu Saito, Hideyuki Sameshima
  • Patent number: 8071468
    Abstract: There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electrically conductive material using electroplating, and polishing the first resist film and the first electrically conductive material layer from the main surface side to flatten their surfaces; and processing, when forming the second redistribution layer, forming the second electrically conductive material layer by growing the second electrically conductive material using electroplating, and polishing the second resist film and the second electrically conductive material layer from the main surface side to flatten their surfaces.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: December 6, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hideyuki Sameshima, Tomoo Ono
  • Publication number: 20100210103
    Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 19, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Hideyuki Sameshima, Tomoo Ono
  • Publication number: 20100203723
    Abstract: There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electrically conductive material using electroplating, and polishing the first resist film and the first electrically conductive material layer from the main surface side to flatten their surfaces; and processing, when forming the second redistribution layer, forming the second electrically conductive material layer by growing the second electrically conductive material using electroplating, and polishing the second resist film and the second electrically conductive material layer from the main surface side to flatten their surfaces.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 12, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Hideyuki Sameshima, Tomoo Ono