Abstract: A reference voltage circuit includes: a first and a second NPN transistor having a collector and a base shorted and diode-connected, the second NPN transistor having an emitter connected to a first potential node and operating at a higher current density; a first resistor connected in series with the first NPN transistor; a second resistor having one end connected to a circuit with the first NPN transistor and the first resistor connected in series; a third resistor having one end connected to the collector of the second NPN transistor; a connection point to which the other ends of the second and the third resistor are connected; an arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal respectively connected to the second resistor, the third resistor, and the connection point; and a current supply circuit connected to the collector of the first NPN transistor.

Abstract: Provided is a shunt regulator including: multiple resistors, connected in series between an output terminal and a ground terminal and constituting a voltage divider circuit; an output transistor, connected between the output terminal and the ground terminal; a first drive circuit, including a first reference voltage circuit which outputs a first reference voltage and an error amplifier, and controlling the output transistor based on a voltage of a first output terminal of the voltage divider circuit; a second drive circuit, controlling the output transistor based on a voltage of a second output terminal of the voltage divider circuit; and an activation control circuit, switching operation of the first drive circuit and the second drive circuit based on the first reference voltage. The second drive circuit has a shorter activation time than the first drive circuit.

Abstract: A reference voltage circuit includes: a first and a second NPN transistor having a collector and a base shorted and diode-connected, the second NPN transistor having an emitter connected to a first potential node and operating at a higher current density; a first resistor connected in series with the first NPN transistor; a second resistor having one end connected to a circuit with the first NPN transistor and the first resistor connected in series; a third resistor having one end connected to the collector of the second NPN transistor; a connection point to which the other ends of the second and the third resistor are connected; an arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal respectively connected to the second resistor, the third resistor, and the connection point; and a current supply circuit connected to the collector of the first NPN transistor.

Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.

Abstract: A voltage regulator which includes a differential amplifier circuit containing a first and second input transistors, controlling a gate-source voltage in each of the first and second input transistors including: a current source configured to drive the differential amplifier circuit; the first input transistor containing a gate; the second input transistor containing a gate; and a voltage controller including at least one of a first voltage control circuit to control a voltage at a tail connection point, a second voltage control circuit to control the voltage at the gate of the first input transistor, a third voltage control circuit to control the voltage at the tail connection point, and a fourth voltage control circuit to control the voltage at the gate of the second input transistor.

Abstract: A voltage regulator which includes a differential amplifier circuit containing a first and second input transistors, controlling a gate-source voltage in each of the first and second input transistors including: a current source configured to drive the differential amplifier circuit; the first input transistor containing a gate; the second input transistor containing a gate; and a voltage controller including at least one of a first voltage control circuit to control a voltage at a tail connection point, a second voltage control circuit to control the voltage at the gate of the first input transistor, a third voltage control circuit to control the voltage at the tail connection point, and a fourth voltage control circuit to control the voltage at the gate of the second input transistor.

Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.

Abstract: Provided is a level shift circuit capable of converting a negative voltage level as well as a positive voltage level. The level shift circuit includes a switching transistor between an input transistor and a load, the switching transistor including a gate connected to a voltage source, and an input negative voltage level is converted into a second negative voltage level based on a voltage of the voltage source and a threshold voltage of the switching transistor.

Abstract: Provided is a signal selection circuit including a control circuit capable of generating a drive signal having a fast rise/fall time. A positive feedback circuit is provided to the control circuit, which generates the drive signal for controlling a plurality of switches configured to switch an input signal to provide the signal to an output terminal.

Abstract: Provided is a level shift circuit capable of converting a negative voltage level as well as a positive voltage level. The level shift circuit includes a switching transistor between an input transistor and a load, the switching transistor including a gate connected to a voltage source, and an input negative voltage level is converted into a second negative voltage level based on a voltage of the voltage source and a threshold voltage of the switching transistor.

Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.

Abstract: Provided is an overheat detection circuit that is capable of quickly outputting an overheated state detection signal in an overheated state without outputting an unintended erroneous output caused by disturbance noise, such as momentary voltage fluctuations in the power supply. The overheat detection circuit includes: a temperature sensor; a comparison section; and a disturbance noise removal section configured to output an overheated state detection signal to an output section after a predetermined delay time has elapsed. The delay time is reduced in proportion to temperature.

Abstract: Provided is an overheat detection circuit that is capable of quickly outputting an overheated state detection signal in an overheated state without outputting an unintended erroneous output caused by disturbance noise, such as momentary voltage fluctuations in the power supply. The overheat detection circuit includes: a temperature sensor; a comparison section; and a disturbance noise removal section configured to output an overheated state detection signal to an output section after a predetermined delay time has elapsed. The delay time is reduced in proportion to temperature.

Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.