Abstract: The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0<x<=1)). The second semiconductor region is formed of silicon (Si).

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

Abstract: The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Sii-xGex (0<x<=1)). The second semiconductor region is formed of silicon (Si).

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

Abstract: A nonvolatile semiconductor storage apparatus includes: a plurality of first wirings; a plurality of second wirings which cross the plurality of first wirings; and a memory cell which is connected between both the wirings at an intersection of the first and second wirings, and includes a variable resistive element operative to store information according to a change in resistance and includes a variable resistive element, wherein the memory cell is formed so that a cross section area of the variable resistive element becomes smaller than a cross section area of the other portion.

Abstract: A method of manufacturing nonvolatile semiconductor memory devices comprises forming a first wiring material; and stacking memory cell materials on the first wiring material, which configure memory cells each including a variable resistor operative to nonvolatilely store information in accordance with variation in resistance. The method also comprises forming a plurality of first parallel trenches in the first wiring material and the stacked memory cell materials, the first trenches extending in a first direction, thereby forming first lines extending in the first direction and memory cell materials self-aligned with the first lines and separated by the first trenches. The method further comprises burying an interlayer insulator in the first trenches to form a block body and stacking a second wiring material on the block body.