Abstract: A 36V electrical apparatus is mountable with both an 18V/36V switchable battery pack and an 18V battery pack. In the case where the 18V/36 V battery pack is connected to the 36V electrical apparatus, first switches are turned off and a second switch is turned on to connect the battery pack in series (36V output). In the case where the 18V battery pack is connected to the 36V electrical apparatus, the first switches are turned on and the second switch is turned off to generate an 18V output, thus making it possible to mount the 18V battery pack to the 36V electrical apparatus. Furthermore, the voltage of the mounted battery pack is determined by a microcomputer, and a motor is set to a star connection by switches in the case of 36V, and to a delta connection in the case of 18V.

Abstract: An arithmetic processing apparatus includes a memory, a first processor coupled to the memory, and a second processor coupled to the memory. The first processor is configured to consecutively issue a plurality of load instructions for reading respective data with respect to the memory. The first processor is configured to determine whether an ordering property is guaranteed, based on values included in the data loaded from the memory. The second processor is configured to issue a store instruction during an execution of the plurality of load instructions with respect to the memory.

Abstract: An amplifier includes a P-type transistor and an N-type transistor that are connected in series, an operation amplifier, a transformer, and a variable attenuator. In the operation amplifier, an output terminal is coupled to a gate side of one of the P-type transistor and the N-type transistor, one of an inverting input terminal and a non-inverting input terminal is coupled to drain sides of both of the P-type transistor and the N-type transistor, and a reference voltage is to be applied to the other of the inverting input terminal and the non-inverting input terminal. In the transformer, a primary coil is coupled to a source side of one of the P-type transistor and the N-type transistor. The variable attenuator is provided between a secondary coil and gate terminals of both of the N-type transistor and the P-type transistor.

Abstract: In an amplifier that uses a transistor, a minimum operation voltage is lowered. An amplifier includes a P-type transistor and an N-type transistor connected in series, and an operational amplifier. An output terminal of the operational amplifier is connected to gates of both the P-type transistor and the N-type transistor. One of an inverting input terminal and a non-inverting input terminal of the operational amplifier is connected to drains of both the P-type transistor and the N-type transistor. Further, a predetermined reference voltage is applied to another of the inverting input terminal and the non-inverting input terminal.

Abstract: An arithmetic processing apparatus includes a memory, a first processor coupled to the memory, and a second processor coupled to the memory. The first processor is configured to consecutively issue a plurality of load instructions for reading respective data with respect to the memory. The first processor is configured to determine whether an ordering property is guaranteed, based on values included in the data loaded from the memory. The second processor is configured to issue a store instruction during an execution of the plurality of load instructions with respect to the memory.

Abstract: In an amplifier that uses a transistor, a minimum operation voltage is lowered. An amplifier includes a P-type transistor and an N-type transistor connected in series, and an operational amplifier. An output terminal of the operational amplifier is connected to gates of both the P-type transistor and the N-type transistor. One of an inverting input terminal and a non-inverting input terminal of the operational amplifier is connected to drains of both the P-type transistor and the N-type transistor. Further, a predetermined reference voltage is applied to another of the inverting input terminal and the non-inverting input terminal.

Abstract: An output signal can be free of any noise component generated from an amplifier disposed in a path, without degradation of the S/N ratio of the output signal. An amplifier includes: a first amplifier that is connected to an input node and generates a first intermediate signal; a feedback resistor that enables feedback of the first intermediate signal to the input node; an attenuator that receives the first intermediate signal and generates a second intermediate signal; a second amplifier that is connected to the input node and generates a third intermediate signal; a third amplifier that is connected to the input node and generates a fourth intermediate signal; and an adder that generates an output signal, using the second intermediate signal, the third intermediate signal, and the fourth intermediate signal.

Abstract: An output signal can be free of any noise component generated from an amplifier disposed in a path, without degradation of the S/N ratio of the output signal. An amplifier includes: a first amplifier that is connected to an input node and generates a first intermediate signal; a feedback resistor that enables feedback of the first intermediate signal to the input node; an attenuator that receives the first intermediate signal and generates a second intermediate signal; a second amplifier that is connected to the input node and generates a third intermediate signal; a third amplifier that is connected to the input node and generates a fourth intermediate signal; and an adder that generates an output signal, using the second intermediate signal, the third intermediate signal, and the fourth intermediate signal.