Abstract: An image compression and expansion apparatus is provided which changes an appearance value of quantization table of quantizer/inverse-quantizer without actually changing values of quantization table by carrying out calculation for every processing. An image compression and expansion apparatus which compresses and expands image data comprises a quantizer which linearly quantizes a Discrete Cosine Transform coefficient by different step size for every coefficient location, an inverse-quantizer which inverse-quantizes coefficients obtained in Huffman decoding, and a quantization table which is necessary for quantization and inverse-quantization process comprising: a register for setting a necessary value in response to an outside signal; a data processing unit for carrying out an operation between values set into the register and values in the quantization table to carry out quantization and inverse-quantization operation.

Abstract: Multiplications in an inverse quantization portion (202) are limited to only multiplications of an effective coefficient (NZ) by a quantization coefficient (Qi) corresponding thereto. An inverse zigzag transform is performed such that fixed values "0", the number of which corresponds to a block of Huffman codes, are previously arranged and the effective coefficient (NZ) is then overwritten in corresponding positions, rather than arranging data including the fixed values "0" and the effective coefficient (NZ). Thus, multiplications of ineffective coefficients are not required and the Huffman codes are decoded at a high speed.

Abstract: A picture encoding device for compressing picture data using the Huffman encoding system includes a grouping portion for recognizing a group to which an AC coefficient belongs, and a data processing unit receiving a run-length, a group number, and an additional bit, which are output from the grouping portion, for recognizing a ZRL* code and an effective coefficient. If the run-length group number (N/S) is an effective symbol, i.e., not a ZRL* code, the data processing unit transmits the effective symbol to a Huffman encoding portion in the next stage. If the N/S comprises a ZRL* code, a ZRL* code count detection counter is incremented. If an EOB* code follows a ZRL* code, ZRL* codes are deleted in a number corresponding to the count value from the ZRL* code count detection counter. The picture encoding device effectively carries out Huffman encoding without encoding unnecessary ZRL* codes in a Huffman encoding system.

Abstract: It is an object of the present invention to simultaneously perform input or output of picture signals for a plurality of components. An image data input interface (310) is capable of input of picture signals (Pm) of three components at its maximum. For example, when picture signals (Pm) of three components are inputted, a clock divider (410) supplies a 1/3 divided signal of a clock signal (CLK) to the image data input interface (310) on the basis of a selection signal (SEL). In the image date input interface (310), the picture signals (Pm) of three components are simultaneously inputted in synchronization with the 1/3 divided signal and they are sent out to a discrete cosine transform unit (4) in synchronization with the clock signal (CLK). The component to which the sent picture signals (Pxy) belong sequentially changes for every 8.times.8 picture elements.

Abstract: A data processor in an image coding apparatus includes a zero detecting circuit for determining if the quantized AC coefficients are zero or not; a counter, that is reset periodically, for counting the quantized AC coefficients that are not zero; a comparator for comparing the count of the counter and a first reference value, and outputting an AC coefficient eliminating signal when the count exceeds the first reference value; and a first logic circuit for forcibly replacing the quantized AC coefficients with zero based on the AC coefficient eliminating signal so that the volume of data of the quantized AC coefficients that are not zero is reduced. The image coding apparatus cuts off some portions for the images having a large volume of codings, and keeps the volume of data below a predetermined maximum.

Abstract: A microcomputer includes a data processor in a bus transfer circuit of the microcomputer and, therefore, simple data processing is enabled when data are transferred to a bus. Further, a microcomputer includes a bit shifter that shifts the data to an upper bit direction or to a lower bit direction while transferring the data to a bus from a memory and, therefore, bit shifting processing, which is a light load, is enabled while transferring data from the memory to a bus. Further, a microcomputer includes a bit processor that performs an operation on an arbitrary bit of data while transferring the data to a bus from the memory and, therefore, bit processing, which is a light load, is enabled while transferring data to a bus from the memory. Furthermore, a microcomputer includes a bit reverser that inverts the positions of bits in a bit sequence and, therefore, bit reversing processing, which is a light load, is enabled.

Abstract: A direct memory access control device is used in a multiprocessor system having a plurality of digital data processors and an external common memory connected in common to those digital data processors through a first bus. In the case of transferring data in a direct memory access mode between processors, the transfer of data between the processors is effected by the control device through a second data bus provided in common to the plurality of digital data processors separately from the first bus. Thus, data can be transferred directly in a direct memory access mode between the processors without using the external memory and high-speed transfer can be realized. In addition, the control device comprises registers for storing the status bits of each digital data processor, such as direct memory access request and acceptance signals, corresponding to each digital data processor. Request and acceptance of direct memory access and transfer of data are effected by monitoring the contents of those registers.

Abstract: A data comparator detects the coincidence or non-coincidence of the logical states between two adjacent bits of the plural bit input data and applies the comparison result signal to a non-coincident bit detection circuit. A mask generator decodes a shift select signal indicating the amount of shift to produce mask data and applies the produced mask data to a non-coincident bit detection circuit. The non-coincident bit detection circuit masks the output of the data comparator on the basis of the mask data and decides whether or not an overflow is produced from the masked output of the data comparator to output the result of decision.

Abstract: An adder circuit for adding two 16-bit data to each other includes 16 full adders and three carry look ahead circuits. A plurality of full adders excluding two ones provided on the least significant bit side and two ones provided on the most significant bit side are classified into three groups. Each of the groups includes four full adders. A single carry look ahead circuit is provided for the four full adders forming each group.

Abstract: There is disclosed an amplifier circuit providing a stable gain independently of fluctuations in power supply voltage, in which resistors (13, 14) and corrective switches (25, 26) having the same construction as analog switches (21 to 24) are provided in a feedback path from an output of an operational amplifier (1) to a negative input thereof, and in which resistors (15, 16) and corrective switches (27, 28) having the same construction as the analog switches (21 to 24) are provided in a reference voltage positive input path from a positive input of the operational amplifier (1) to a reference voltage (VR). An L level logical signal is applied to control inputs (C) of the corrective switches (25 to 28) and an H level logical signal is applied to control inputs (D) thereof. The corrective switches (25 to 28) are constantly set to an ON-state under the same conditions as the analog switches (21 to 24) in the ON-state.

Abstract: A microprocessor with an improved register part is disclosed. The register part includes a plurality of registers for holding data and adding circuits connected to the outputs of predetermined two registers. Adding circuits are provided as a preceding operation circuit and a part of the operation to be executed in an ALU or a multiplier is carried out in the preceding operation circuit. At the time two data to be used in an operation are applied to the predetermined two registers, addition is started in the preceding operation circuit. Therefore, the number of instructions required for carrying out the operation is reduced thereby realizing faster processing.

Abstract: A processing unit containing a DMA controller comprises a 2nb (n.gtoreq.1) processor data bus (6), a 2nb DMA data bus (7), a 2nb (m.gtoreq.1) processor address bus (8), and a 2nb DMA address bus (9). These buses have a plurality of latch circuits (51-54) respectively connected thereto. One of the processor and DMA data latched in each latch circuit, and one of the processor and DMA addresses are selected by a first multiplexer (55, 56). The 2nb data and 2mb data from the output of the first multiplexer and the outputs of the latch circuits are divided into sets of nb and mb, respectively; thus they are given in the form of 3 inputs to a second multiplixer (57-60). When the processor and the DMA controller concurrently operate, data and address are transferred without keeping one of them waiting.

Abstract: A novel array processor is provided with a plurality of local memories in each data processing element and allows these local memories to be accessed simultaneously, so that a plurality of local memories provided for each data processing element can simultaneously be accessed. The array processor is also has one local memory which is provided with a plurality of output ports for each data processing element, so that all the output ports can simultaneously be accessed, permitting the local memory unit to be accessed simultaneously through a plurality of output ports. The array processor of the present invention decreases the number of memory accesses in each data processing element, with the cumulative effect of achieving a faster speed for the entire data processing system.

Abstract: A device for finding a moving average of a signal applied from a signal source includes a first delay circuit for delaying input data sampled in a predetermined sampling period by a time period corresponding to N sampling periods where N is an integer, an accumulator for receiving an output of the first delay circuit and input data to store data of (N-1) terms, and a divider for dividing an output of the accumulator by a coefficient (N-1). The accumulator includes an adder, a second delay circuit for delaying an output of the adder by a time period corresponding to one sampling period, and a subtractor for carrying out subtraction between the output of the first delay circuit and that of the second delay circuit to supply a result of the subtraction to the divider. The adder adds input data and an output of the subtractor. This configuration enables implementation of the device for performing fast moving average processing with a simple configuration.

Abstract: An SR latch is provided, which comprises a D-type latch and a logic circuit connected between data and sense input of the D-type latch and set and reset input terminals of the SR latch circuit. The logic circuit establishes the logic levels of signals applied to the data and sense inputs of the D-type latch such that said SR latch circit can assume one of set, reset and hold states depending on the combination of the logic levels of the signals applied to the set and reset input terminals.

Abstract: A test circuit for logic circuits of the present invention is constructed with a register for storing data to be operated in the logic circuits and its operation results and interface circuit is connected to the register through an internal bus and is controlled from external terminals. The data to be operated on by the logic circuits is set in the register directly from the interface circuit for operation, and the operation result data stored in the register are outputted to the external source directly from the interface circuit. By adopting such a configuration, since the data to be operated in the logic circuits can be transferred from the interface circuit to the register, and data of the operation result stored in the register can be transferred to the interface circuit without executing a data transfer instruction, the logic circuits can be tested readily by giving the data to the logic circuits from the external and outputting its operation results to the external.

Abstract: A priority order decomposing apparatus converting binary data of a plurality of bits into data wherein "1"s other than "1" of the bit whose priority order is the highest are removed, a circuit for checking whether or not "1" exists is installed for each group of bits taken as a unit of converting process. When "1" exists, this is transmitted directly to the low-order-bit side to immediately set the lower-order bits to "0". This permits the operating speed to be made faster.

Abstract: A plurality of testing circuits formed of parallel registers are incorporated in a plurality of circuit portions constituting a data processing circuit, the circuit portions having different number of bits to be processed. Each parallel register comprises scan latch circuits and latch circuits. The sum of the number of the scan latch circuits and that of the latch circuits being equal to the number of output terminals of the circuit portion having maximum number of bits to be processed. Each scan latch circuit has a first input terminal connected to an output terminal of the corresponding circuit portion, a second input terminal connected to the input terminal of the circuit portion, and an output terminal connected to the input terminal of another circuit portion, respectively. The control terminals are connected together in each register to receive control signals.

Abstract: A plurality of testing circuits formed of parallel registers are incorporated between a plurality of circuit portions constituting a data processing circuit. Each parallel register comprises scan latch circuits whose number corresponding to the number of sets of input and output terminals of the circuit portion. A first input terminal of each scan latch circuit is connected to an output terminal of the corresponding circuit portion, a second input terminal is connected to an input terminal of the corresponding circuit portion, an output terminal is connected to an input terminal of another circuit portion, respectively, control terminals of the scan latch circuits are connected together in each register to which a control signal is inputted. The testing circuit serves to test the circuit portion or operate the circuit portion upon reception the control signal corresponding to the test mode or the operation mode.

Abstract: The present invention relates to a circuit for detecting an overflow when data is shifted by a shifter. The circuit of the present invention makes possible the detection of an overflow during 1 clock period. In addition, it compares the magnitude of the bit string signal, obtained by passing data through a priority order decomposing circuit with the magnitude of the signal obtained by passing the shift number through a decoder.