Abstract: A secure communication system is provided, in which a common cryptographic key is generated using the biological information simultaneously acquirable by multiple communication devices. The communication system includes multiple separated communication devices. The communication device generates the same common key based on the feature element of simultaneously acquirable biological information, and performs encryption and decryption using the common key. The communication device includes a biological information acquiring unit to acquire the feature element of the biological information; a common key generation unit to generate the common key; an encryption/decryption unit to encrypt transmit information and to decrypt receive information with the common key; and a communication unit to receive the transmit information and to transmit the receive information.

Abstract: Provided is a technology for a technology for easily inhibiting a wireless signal from being spoofed. A wireless communication system includes a beacon device and an information processing terminal. The beacon device includes a first communication circuit for transmitting a beacon signal to the information processing terminal in accordance with a predetermined transmission interval pattern. The information processing terminal includes a second communication circuit, a first storage device, and a control device. The second communication circuit receives the beacon signal from the beacon device. The first storage device stores the predetermined transmission interval pattern. The control device authenticates the beacon device by comparing a reception interval pattern of the beacon signal received by the second communication circuit with the predetermined transmission interval pattern stored in the first storage device.

Abstract: A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer such as a pad, wiring layer or inductor having a predetermined pattern, formed on an interlayer insulation film formed on the above shield/planarization portion. Just under the metal layer is disposed the shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded.

Abstract: A semiconductor device is arranged by having a shield/planarization portion including a silicided active region formed on the main surface of a semiconductor substrate and a non-active region provided by device-isolation on the surface, and a metal layer such as a pad, wiring layer or inductor having a predetermined pattern, formed on an interlayer insulation film formed on the above shield/planarization portion. Just under the metal layer is disposed the shield/planarization portion in which the area ratio of the active region to the non-active region is given in a predetermined proportion and the active region is electrically grounded.

Abstract: In a variable frequency divider formed of a latch train, a frequency division ratio is set through selective invalidating a feedback signal to a first stage latch from the last stage latch. A size of MOS (metal-insulator-semiconductor) transistors for switching the division ratio is made larger than that of other MOS transistors in differential stages in the last stage latch circuit. Further, differential signals are transmitted as feedback signals to the first stage latch circuit. A F/(F+1) prescaler which operates stably with a low current consumption under a low power supply voltage condition is implemented.

Abstract: In a variable frequency divider formed of a latch train, a frequency division ratio is set through selective invalidating a feedback signal to a first stage latch from the last stage latch. A size of MOS (metal-insulator-semiconductor) transistors for switching the division ratio is made larger than that of other MOS transistors in differential stages in the last stage latch circuit. Further, differential signals are transmitted as feedback signals to the first stage latch circuit. A F/(F+1) prescaler which operates stably with a low current consumption under a low power supply voltage condition is implemented.