Patents by Inventor Hideyuki Yamada

Hideyuki Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6613339
    Abstract: An object of the present invention is to provide a cosmetic for nail that suppresses dryness of nails, that makes nails hard to fracture, that makes nails glossy as they are, that keeps or improves healthiness of nails, and that is highly safe. The cosmetic for nail is provided by adding 0.02 to 20% by weight of sericin as an effective ingredient additionally to the conventional cosmetic ingredients.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: September 2, 2003
    Assignees: Teikoku Seiyaku Co., Ltd., Seiren Co., Ltd.
    Inventors: Hideyuki Yamada, Keiko Yamasaki, Keiji Nozaki
  • Publication number: 20030134388
    Abstract: An object of the present invention is to provide a medium supplement for animal cell culture and an animal cell culture medium. The present invention relates to a medium supplement for animal cell culture comprising sericin or a sericin derivative and an animal cell culture medium comprising at least said medium supplement and a basal medium composition.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 17, 2003
    Inventors: Masahiro Sasaki, Hideyuki Yamada, Katsue Osada, Satoshi Terada
  • Publication number: 20010053759
    Abstract: The present invention provides a skin cancer preventive agent that inhibits the promotion of carcinogenesis of skin cancer while having high levels of safety and stability as well as being free of adverse side effects. The present invention is characterized by containing sericin.
    Type: Application
    Filed: May 24, 2001
    Publication date: December 20, 2001
    Applicant: KABUSHIKI KAISHA AIOI HAKKO & SEIREN KABUSHIKI KAISHA
    Inventors: Zongxuan Jin, Koichiro Muramatsu, Hideyuki Yamada, Naozumi Fuwa, Hiroshige Hibasami
  • Patent number: 6165982
    Abstract: This invention relates to a composition useful as an antioxidant or an inhibitor for tyrosinase activity which comprises as an active ingredient a sufficient amount of sericin to exert an antioxidizing ability or an inhibiting action on tyrosinase activity and this composition is applicable as an antioxidant or a tyrosinase activity inhibitor in the field of medicines, quasi-drugs, medicines for external use, cosmetics, foods, food additives or the like.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: December 26, 2000
    Assignee: Seiren Co., Ltd.
    Inventors: Hideyuki Yamada, Naozumi Fuwa, Masakazu Nomura
  • Patent number: 5958021
    Abstract: An input-output interface circuit operative in three different modes which utilizes a first signal selector, operative selectively in an external signal output mode and an internal signal transmission mode, having one output terminal to which a signal is transmitted from a signal processor and first and second output terminals, a second signal selector, operative selectively in an external signal input mode and an internal signal transmission mode, having one output terminal through which a signal input to the signal processor is transmitted and first and second output terminals, the first output terminal of the first signal selector being connected to the external input-output terminal by an external output signal transmission channel; the second output terminal of the first signal selector being connected to the first input terminal of the second signal selector by an internal signal transmission channel; and the external input-output terminal being connected to the second input terminal of the second signa
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: September 28, 1999
    Assignee: Mazda Motor Corporation
    Inventors: Kiyoyuki Tsuchiyama, Hideyuki Yamada, Kouichi Nakamura
  • Patent number: 5886565
    Abstract: A reference voltage generating circuit is provided with a reference voltage output terminal, a voltage dividing circuit that divides a voltage supplied from a power source, and an integrating circuit having a given time constant, for integrating a voltage of the divided voltage output terminal of the voltage dividing circuit and generating a reference voltage as a result of integration to the reference voltage output terminal. A high-speed charging circuit is connected to the reference voltage output terminal, for charging the integrating circuit at a high speed when the power source is turned on, to elevate a voltage of the reference voltage output terminal at a speed higher than a speed determined by the time constant of the integrating circuit.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: March 23, 1999
    Assignee: Yamaha Corporation
    Inventors: Shoji Yasui, Hideyuki Yamada
  • Patent number: 5801407
    Abstract: An analog-circuit block, which is fabricated on a chip of a semiconductor integrated circuit, is configured by a plurality of analog cells each having a desired function such as the function of an operational amplifier. The analog cells are standardized with respect to the height thereof. Two power-source wires are provided respectively in an upper-end section and a lower-end section of the analog-circuit block, so that they are commonly used by the analog cells. In the analog cell, input/output wires are placed in a direction perpendicular to the power-source wires. For example, two input wires are provided to input signals for two inputs of an operational amplifier while one output wire is provided to provide an output signal, wherein one of the two input wires is partially connected to the output wire. Further, it is possible to provide a dummy wire which is placed in parallel with the output wire, wherein a midpoint of the output wire is connected to a midpoint of the dummy wire.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: September 1, 1998
    Assignee: Yamaha Corporation
    Inventor: Hideyuki Yamada
  • Patent number: 5728461
    Abstract: Functional fiber products are provided.The functional fiber products are those adhered thereto a protein containing 20% to 40% by weight of serine as an amino acid component and those adhered thereto sericin and deacetylated chitin.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: March 17, 1998
    Assignee: Seiren Co., Ltd.
    Inventors: Akihiro Nogata, Hideyuki Yamada, Masakazu Nomura
  • Patent number: 5480508
    Abstract: A prepreg tape is firstly prepared by bonding prepreg layer to a backing paper and then the prepreg tape is cut to a depth enough to cut the prepreg tape but not the backing paper. A unnecessary portion of the prepreg tape is removed from the backing paper to obtain a cut prepreg tape. A laminating attachment is moved in a predetermined direction while urging the prepreg tape against the surface of an operating table. The cut prepreg tape is peeled off from the backing paper and the peeled off prepreg tape is bonded to the operating table. The cut prepreg tapes are successively oriented in a predetermined direction and juxtaposed to form a laminated sheet. When the sheet is mounted on a mold of a predetermined shape. When the impregnated thermosetting resin is perfectly cured under heat and pressure a product useful for assembling various vehicles can be obtained.
    Type: Grant
    Filed: August 18, 1994
    Date of Patent: January 2, 1996
    Assignees: Toshiba Kikai Kabushiki Kaisha, Fuji Jukogyo Kabushiki Kaisha
    Inventors: Takao Manabe, Yuhei Yamakawa, Shoichi Shin, Hideyuki Yamada, Mitsuo Nagashima, Mitsunori Kokubo, Masafumi Tsunada, Yasuhiko Nagakura, Yukio Nakajima, Tomohiro Inoue, Kiyoshi Kondo
  • Patent number: 5397415
    Abstract: A prepreg tape is firstly prepared by bonding prepreg layer to a backing paper and then the prepreg tape is cut to a depth enough to cut the prepreg tape but not the backing paper. An unnecessary portion of the prepreg tape is removed from the backing paper to obtain a cut prepreg tape. A laminating attachment is moved in a predetermined direction while urging the prepreg tape against the surface of an operating table. The cut prepreg tape is peeled off from the backing paper and the peeled off prepreg tape is bonded to the operating table. The cut prepreg tapes are successively oriented in a predetermined direction and juxtaposed to form a laminated sheet. The sheet is that mounted on a mold of a predetermined shape. When the impregnated thermosetting resin is perfectly cured under heat and pressure, a product useful for assembling various vehicles can be obtained.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: March 14, 1995
    Assignees: Toshiba Kikai Kabushiki Kaisha, Fuji Jukogyo Kabushiki Kaisha
    Inventors: Takao Manabe, Yuhei Yamakawa, Shoichi Shin, Hideyuki Yamada, Mitsuo Nagashima, Mitsunori Kokubo, Masafumi Tsunada, Yasuhiko Nagakura, Yukio Nakajima, Tomohiro Inoue, Kiyoshi Kondo
  • Patent number: 5386623
    Abstract: A multi-chip module and a process for manufacturing the same comprises at least first and second semiconductor chips each formed with a plurality of semiconductor elements on their circuit forming surfaces and having different functions, mounted on a substrate. An insulating film is formed over the circuit forming surfaces of the first and second semiconductor chips. First and second connecting holes are formed in the insulating film over the circuit forming surfaces of the first and second semiconductor chips, respectively. A wiring layer is formed across the first and second connection holes so as to connect the first and second semiconductor chips electrically.
    Type: Grant
    Filed: November 7, 1991
    Date of Patent: February 7, 1995
    Assignees: Hitachi, Ltd., Hitachi Computer Engineering Co., Ltd.
    Inventors: Yoshihiko Okamoto, Hideyuki Yamada
  • Patent number: 5288357
    Abstract: In a method and apparatus for laminating prepreg sheets, a plurality of heaters and a plurality of fans are installed beneath an operating table and a table temperature sensor and a room temperature sensor are provided in and above the operating table respectively. The heaters, fans, table temperature sensor and the room temperature sensor are controlled by a temperature control device. A face sheet is mounted on the operating table and the prepreg sheets are laminated while maintaining the temperature of the face sheet at a higher value than the temperature of the prepreg sheets, whereby the adhesive force of the face sheet becomes higher than that of a carrier sheet so that the prepreg sheet can be accurately bonded to the face sheet.
    Type: Grant
    Filed: April 7, 1992
    Date of Patent: February 22, 1994
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Hideyuki Yamada, Masafumi Tsunada, Yasuhiko Nagakura, Soichi Shin
  • Patent number: 4421361
    Abstract: A brake fluid pressure control apparatus in a skid control system for a vehicle having at least one wheel and a brake for the wheel includes a control unit for measuring the skid condition of the wheel; a fluid pressure control valve device arranged between a master cylinder and a wheel cylinder of a brake for the wheel, the fluid pressure control valve device receiving control signals of the control unit to control the brake fluid pressure to the wheel cylinder; a hydraulic reservoir which, when the brake fluid pressure to the wheel cylinder is decreased with control of the fluid pressure control valve device, reserves the brake fluid discharged through the fluid pressure control valve device from the wheel cylinder; a pressure fluid supply conduit connecting the master cylinder with the fluid pressure control valve device; a fluid pump with motor receiving a pump drive signal of the control unit for returning the brake fluid from the hydraulic reservoir into the pressure fluid supply conduit; a switching ar
    Type: Grant
    Filed: December 8, 1981
    Date of Patent: December 20, 1983
    Assignee: Nippon Air Brake Co., Ltd.
    Inventors: Tetsuro Arikawa, Hideyuki Yamada
  • Patent number: 4376726
    Abstract: An improved method of manufacturing a composition for bonded magnets in which deterioration of the composition due to heat is prevented, while uniform dispersion of ferrite powder is achieved for stabilization of physical properties and various characteristics of the resultant bonded magnets.
    Type: Grant
    Filed: March 16, 1981
    Date of Patent: March 15, 1983
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadashi Sakaira, Hideyuki Yamada, Tamotsu Wakahata