Abstract: A disk apparatus has a reading portion which reads out a plurality of frames stored in a disk and outputs a read signal, a detecting portion which determines that part of the read signal is identical to a frame synchronization code signal or determines that a deviation between a symbol of part of the read signal and a symbol of the frame synchronization code signal is within a certain time range to detect the frame synchronization code signals from the read signal, and a reproducing portion which reproduces the read signal in synchronization with the detected frame synchronization code signals.

Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

Abstract: A run length limited code recording/reproduction apparatus according to an aspect of this invention includes a generation unit for generating a plurality of different code sequences which have recording densities that gradually become higher, and a recording unit for recording the plurality of different code sequences generated by the generation unit on a plurality of successive subfields in a test data field of an information storage medium.

Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

Abstract: A digital signal decoding device according to an aspect of the present invention is a digital signal decoding device for generating a binary code sequence by maximum likelihood estimation from a convolutionally encoded input signal sequence, includes an add-compare-select unit configured to compare only two metric values one unit time before the calculation time of a predetermined branch metric value calculated from the input signal sequence at two successive times at each time, to add the predetermined branch metric value to the two metric values independently of the compare process, to select one of the two sums in accordance with the comparison result of the two metric values, and to output the selected value as a metric value to be used at the next time.

Abstract: A focus offset setting portion gives a predetermined quantity of offset to a focus control quantity used to reduce a focus error signal to zero based on the focus error signal generated by a focus error generation portion, and outputs a result. An adaptive equalizer including an adaptive control portion and an FIR filter subjects a reproduction signal RF provided from an optical pickup to waveform equalization based on a signal decoded by a Viterbi decoder. A controller obtains an optimum point of a focus offset by using a tap coefficient of the adaptive equalizer, and changes a set value of a focus offset setting portion.

Abstract: A run length limited code recording/reproduction apparatus according to an aspect of this invention includes a generation unit for generating a plurality of different code sequences which have recording densities that gradually become higher, and a recording unit for recording the plurality of different code sequences generated by the generation unit on a plurality of successive subfields in a test data field of an information storage medium.

Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

Abstract: A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.

Abstract: A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.

Abstract: A data discrimination apparatus which is capable of correcting a decrease in amplitude of a signal to be data discriminated by a correction value so as to correct the bit itself which was used as a target bit to determine the correction value. A decision circuit preliminarily classifies an equalizer output into symbols "0" and "1" to obtain a run length of the symbol "0" with respect to a given symbol "1" (the target bit). A correction value generating circuit includes a memory device which contains correction values in correspondence with all the possible values of the run length, and outputs one of the correction values out of the memory device in response to an output from the decision circuit. A delay circuit delays the equalizer output by a time which is required until the correction value is output. An operation circuit adds the selected correction value to the delayed equalizer output, to correct the same.

Abstract: A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected.

Abstract: An AGC circuit is provided with a variable gain amplifier which changes an amplification gain of an input signal in accordance with an instruction; an extraction unit for extracting a value of an output of the variable gain amplifier at a predetermined interval; and a variable gain control unit for instructing the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the value extracted by the extraction unit.