Patents by Inventor Hideyuki Yoko

Hideyuki Yoko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10217525
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Imc.
    Inventor: Hideyuki Yoko
  • Publication number: 20180330799
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hideyuki Yoko
  • Publication number: 20180240534
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Application
    Filed: September 25, 2017
    Publication date: August 23, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hideyuki Yoko
  • Patent number: 10056157
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: August 21, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Hideyuki Yoko
  • Publication number: 20180174631
    Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventor: Hideyuki Yoko
  • Patent number: 9911480
    Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 6, 2018
    Assignee: Longitude Semiconductor S.a.r.l
    Inventor: Hideyuki Yoko
  • Patent number: 9805828
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 31, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Hideyuki Yoko
  • Publication number: 20150364179
    Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Inventor: Hideyuki Yoko
  • Patent number: 9123399
    Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: September 1, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hideyuki Yoko
  • Patent number: 9087571
    Abstract: A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: July 21, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Hideyuki Yoko, Naohisa Nishioka, Chikara Kondo, Ryuji Takishita
  • Publication number: 20140344612
    Abstract: To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit. 1.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 20, 2014
    Inventors: Hideyuki YOKO, Kentaro Hara, Ryuji Takishita
  • Patent number: 8803545
    Abstract: To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: August 12, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Hideyuki Yoko, Kentaro Hara, Ryuji Takishita
  • Publication number: 20140169057
    Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.
    Type: Application
    Filed: February 21, 2014
    Publication date: June 19, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8687449
    Abstract: A semiconductor device according to the present invention includes plural core chips CC0 to CC7 to which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CC0 to CC7. The interface chip IF receives address information ADD for specifying a memory cell, and supplies in common a part of the address information to the core chips CC0 to CC7 as chip selection information SEL to be compared with the chip identification information LID. With this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for a conventional semiconductor memory device can be used.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Publication number: 20140056086
    Abstract: A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.
    Type: Application
    Filed: November 1, 2013
    Publication date: February 27, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hideyuki Yoko, Naohisa Nishioka, Chikara Kondo, Ryuji Takishita
  • Patent number: 8599641
    Abstract: Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: December 3, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hideyuki Yoko, Naohisa Nishioka, Chikara Kondo, Ryuji Takishita
  • Patent number: 8547775
    Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: October 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8542516
    Abstract: A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8498831
    Abstract: To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: July 30, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Akira Ide, Hideyuki Yoko, Kayoko Shibata, Kenichi Tanamachi, Takanori Eguchi, Yasuyuki Shigezane, Naoki Ogawa, Kazuo Hidaka
  • Patent number: RE46141
    Abstract: A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 6, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Hideyuki Yoko, Ryuuji Takishita