Patents by Inventor Hideyuki Yokou

Hideyuki Yokou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Calibration circuit
    Patent number: 7986150
    Abstract: To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, both a control signal ACT1 and ACT2 is activated, and a calibration operation is performed for both the first replica buffer and the second replica buffer in parallel.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 26, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yokou
  • CALIBRATION CIRCUIT
    Publication number: 20080122450
    Abstract: To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, both a control signal ACT1 and ACT2 is activated, and a calibration operation is performed for both the first replica buffer and the second replica buffer in parallel.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hideyuki YOKOU
  • Semiconductor memory device and method of controlling the same
    Patent number: 6809946
    Abstract: In a semiconductor memory device including a bank equipped having a predetermined memory capacity, a sub amplifier block is disposed at a center of the bank divided into two sections. The sub amplifier block includes a plurality of sub amplifiers connected to sense amplifier sets disposed in the two memory regions through an LIO and a sub amplifier control circuit for controlling the sub amplifiers. If the sub amplifier control circuit selects a word line, a control operation is performed to activate only one side of the sub amplifiers positioned on both sides of the word line to thereby reduce the power consumed for activating the sub amplifiers.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: October 26, 2004
    Assignees: Elpida Memory, Inc., Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Fujisawa, Hideyuki Yokou
  • Semiconductor memory device and method of controlling the same
    Publication number: 20040004890
    Abstract: In a semiconductor memory device including a bank equipped having a predetermined memory capacity, a sub amplifier block is disposed at a center of the bank divided into two sections. The sub amplifier block includes a plurality of sub amplifiers connected to sense amplifier sets disposed in the two memory regions through an LIO and a sub amplifier control circuit for controlling the sub amplifiers. If the sub amplifier control circuit selects a word line, a control operation is performed to activate only one side of the sub amplifiers positioned on both sides of the word line to thereby reducce the power consumed for activating the sub amplifiers.
    Type: Application
    Filed: May 22, 2003
    Publication date: January 8, 2004
    Inventors: Hiroki Fujisawa, Hideyuki Yokou