Abstract: To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Gate of N1 is connected to IN. Drain of N1 is connected to OUT. Cathode of diode D1 is connected to power supply, anode of D1 being connected to OUT. Cathode of diode D2 is connected to OUT, anode of D2 being grounded. When seen from a direction perpendicular to a substrate on which an inverter circuit is formed, a projection plane of a region of a p+ diffusion layer of D1 includes a projection plane of a region of an n+ diffusion layer of N, and a projection plane of a region of an n+ diffusion layer of the diode D2 includes a projection plane of a region of a p+ diffusion layer of P1.

Abstract: To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Drain of P1 is connected to output terminal OUT. Source and back gate of N-channel transistor N1 are grounded. Gate of N1 is connected to IN. Drain of N1 is connected to OUT. Cathode of diode D1 is connected to power supply, anode of D1 being connected to OUT. Cathode of diode D2 is connected to OUT, anode of D2 being grounded. When seen from a direction perpendicular to a substrate on which an inverter circuit is formed, a projection plane of a region of a p+ diffusion layer 32 of D1 includes a projection plane of a region of an n+ diffusion layer 24 of N1, and a projection plane of a region of an n+ diffusion layer 41 of the diode D2 includes a projection plane of a region of a p+ diffusion layer 14 of P1.

Abstract: A latch circuit includes a first circuit configured to generate a first output signal from a first input signal and to generate a second output signal from a second input signal; and a first logic circuit connected with the first circuit, and configured to generate a first logic output signal in response to the first output signal and to generate a second logic output signal in response to the second output signal. A first threshold of the first circuit when the first output signal is generated from the first input signal and a second threshold of the first circuit when the second output signal is generated from the second input signal are different from each other.