Patents by Inventor Hien Boon Tan
Hien Boon Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080061414Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. Then, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.Type: ApplicationFiled: August 29, 2007Publication date: March 13, 2008Applicant: United Test and Assembly Center Ltd.Inventors: Danny RETUTA, Hien Boon Tan, Anthony Sun, Mary Annie Cheong
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Publication number: 20080054435Abstract: A stacked die semiconductor package that includes a substrate with a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions. The package also includes a first semiconductor chip having a non-active surface in contact with the adhesive portions, and an active surface being electrically connected to the substrate. In the package, a second semiconductor chip the non-active surface of the second semiconductor chip is attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween. The active surface of the second semiconductor chip is electrically connected to the substrate. An encapsulant material covers the first and second semiconductor chips and their associated electrical connections. The encapsulating material fills the at least one gap between the plurality of adhesive portions and thereby encapsulates the second semiconductor chip and its associated electrical connection.Type: ApplicationFiled: August 29, 2007Publication date: March 6, 2008Applicant: United Test and Assembly Center, Ltd.Inventors: Gaurav MEHTA, Hien Boon Tan, Susanto Tanary, Mary Annie Cheong, Anthony Sun, Chuen Wang
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Patent number: 7339278Abstract: A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates a support which securely holds the chip in place with adhesive for assembly.Type: GrantFiled: September 28, 2006Date of Patent: March 4, 2008Assignee: United Test and Assembly Center Ltd.Inventors: Henry Iksan, Seong Kwang Brandon Kim, Susanto Tanary, Hien Boon Tan, Yi Sheng Anthony Sun
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Patent number: 7323769Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.Type: GrantFiled: May 8, 2006Date of Patent: January 29, 2008Assignee: United Test and Assembly Center Ltd.Inventors: Hien Boon Tan, Anthony Yi Sheng Sun, Francis Koon Seong Poh
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Publication number: 20070164425Abstract: This invention includes a heat sink structure for use in a semiconductor package that includes a ring structure with down sets and a heat sink connected to the ring structure. The down sets can be slanted or V-shaped. The invention also includes a method of manufacturing a semiconductor package that includes inserting a substrate with an attached semiconductor chip in a first mold portion, placing a heat sink structure on top of a portion of the substrate, placing a mold release film onto a second mold portion, clamping a second mold portion onto a portion of the heat sink structure, injecting an encapsulant into a mold cavity, wherein the encapsulant surrounds portions of the substrate, semiconductor chip and heat sink structure, curing the encapsulant, whereby the heat sink structure adheres to the encapsulant and singulating the encapsulated assembly to form a semiconductor package.Type: ApplicationFiled: July 31, 2006Publication date: July 19, 2007Inventors: Ravi Kanth Kolan, Danny Vallejo Retuta, Hien Boon Tan, Anthony Yi Sheng Sun, Susanto Tanary, Patrick Tse Hoong Low
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Publication number: 20070132081Abstract: A semiconductor package including a first substrate having a die receiving area, a first adhesive layer, a window opening, and a plurality of conductive traces, a first semiconductor die having two sides and with an electrically active side mounted to the substrate through the first adhesive layer, a second adhesive layer having a first side attached to an electrically inactive side of the first semiconductor die, a second substrate having a die receiving area and a plurality of conductive traces and terminals, a last adhesive layer having a first side attached to a side of the second substrate with the terminals, a last semiconductor die having two sides and with an electrically inactive side being mounted to the second side of the third adhesive layer, and an electrically active side being electrically coupled to the conductive traces of the first or second substrate directly or through a redistribution device, and an encapsulant to encapsulate the semiconductor dies and electrical coupling, and signal tranType: ApplicationFiled: March 3, 2005Publication date: June 14, 2007Applicant: UNITED TEST AND ASSEMBLY CENTER LIMITEDInventors: Chuen Khiang Wang, Hien Boon Tan, Koon Hwee Joanne Teo, Sin Nee Song, Koon Lua
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Publication number: 20070069371Abstract: A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates a support which securely holds the chip in place with adhesive for assembly.Type: ApplicationFiled: September 28, 2006Publication date: March 29, 2007Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Henry IKSAN, Seong Kwang Brandon KIM, Susanto TANARY, Hien Boon TAN, Yi Sheng Anthony SUN
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Patent number: 7109570Abstract: An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.Type: GrantFiled: March 30, 2004Date of Patent: September 19, 2006Assignee: United Test and Assembly Test Center Ltd.Inventors: Rodel Manalac, Hien Boon Tan, Francis Poh, Jaime Siat, Roland Cordero
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Publication number: 20060192292Abstract: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.Type: ApplicationFiled: October 28, 2005Publication date: August 31, 2006Inventors: Chuen Khiang Wang, Hien Boon Tan, Anthony Yi Sheng Sun, Sin Nee Song, Steven Yu Yao, Hua Hong Tan
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Patent number: 6876069Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.Type: GrantFiled: June 16, 2003Date of Patent: April 5, 2005Assignee: ST Assembly Test Services Pte Ltd.Inventors: Jefferey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han
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Publication number: 20040124508Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.Type: ApplicationFiled: November 26, 2003Publication date: July 1, 2004Applicant: UNITED TEST AND ASSEMBLY TEST CENTER LTD.Inventors: Hien Boon Tan, Anthony Yi Sheng Sun, Francis Koon Seong Poh
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Publication number: 20040104457Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.Type: ApplicationFiled: November 26, 2003Publication date: June 3, 2004Applicant: UNITED TEST AND ASSEMBLY TEST CENTER LTD.Inventors: Hien Boon Tan, Anthony Yi Sheng Sun
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Publication number: 20040070055Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.Type: ApplicationFiled: June 16, 2003Publication date: April 15, 2004Applicant: ST ASSEMBLY TEST SERVICES PTE LTDInventors: Jeffrey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han
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Patent number: 6630373Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.Type: GrantFiled: February 26, 2002Date of Patent: October 7, 2003Assignee: St Assembly Test Service Ltd.Inventors: Jeffrey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han
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Publication number: 20030160309Abstract: A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.Type: ApplicationFiled: February 26, 2002Publication date: August 28, 2003Applicant: St Assembly Test Services Pte LtdInventors: Jeffrey D. Punzalan, Hien Boon Tan, Zheng Zheng, Jae Hak Yee, Byung Joon Han
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Patent number: 6420779Abstract: An embodiment of the invention in a quad flat no-lead package is described. The package is produced by encapsulating an integrated circuit chip, a die pad to which the chip is affixed, and leads which are connected to the chip in a molding compound. Leads are positioned on all four sides of the package, the exposed (bottom) portions of the leads are coplanar with the bottom of the package, and the leads do not extend, or extend only slightly, beyond the area of the package. The package includes a die pad also having an exposed (bottom) portion that is coplanar with the bottom of the package. The top portions of the leads are coplanar with the top surface of the die pad, and are flat.Type: GrantFiled: September 14, 1999Date of Patent: July 16, 2002Assignee: ST Assembly Test Services Ltd.Inventors: Nirmal K. Sharma, Rahamat Bidin, Hien Boon Tan