Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

Abstract: Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

Abstract: A method to help developers manage ID values for big systems includes assigning an array with N values, an index is the value of allocated pointer, initially 0. Anytime an allocate function is called, this index value increases by 1 and is reset to 0 when the previous value is (N?1). The system calculate the fit position to assign released value in the array which is ready for allocation. If the system needs more than N values, the allocation request will be rejected. The method is useable for high performance and can be acceptable for big systems depending on the strategy to manage id values from the developer.

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: According to one general aspect, an apparatus may include a processor coupled with a memory controller via a first path and a second path. The first path may traverse a coherent interconnect that couples the memory controller with a plurality of processors, including the processor. The second path may bypass the coherent interconnect and has a lower latency than the first path. The processor may be configured to send a memory access request to the memory controller and wherein the memory access request includes a path request to employ either the first path or the second path. The apparatus may include the memory controller configured to fulfill the memory access request and, based at least in part upon the path request, send at least part of the results of the memory access to the processor via either the first path or the second path.

Abstract: A nipple cushion formed as part of an insert for a breast-receiving funnel-shaped membrane of a breast pump. The nipple cushion may include an adhesive to form a temporary bond to any type of a breast pump cushion. Such a nipple cushion of the present invention absorbs any friction created by the movement between the breast pump and the user's breast, with the aid of the material that constitutes the nipple cushion.

Abstract: A method includes: receiving a coherent request from a requester; looking up a state array of a snoop filter table corresponding to an index identified by the coherent request; determining state information corresponding to the coherent request; and determining to access one or more address tag arrays of the snoop filter table based on one or more of the state information, the requester, and a type of the coherent request.

Abstract: A method includes: receiving a coherent request from a requester; looking up a state array of a snoop filter table corresponding to an index identified by the coherent request; determining state information corresponding to the coherent request; and determining to access one or more address tag arrays of the snoop filter table based on one or more of the state information, the requester, and a type of the coherent request.

Abstract: A method to provide a user an informational tour of a location includes emitting a position signal from a wireless device at a position along the informational tour, detecting the position signal with an electronic device, and outputting information based upon the position signal with the electronic device.

Abstract: A portable foldable infant bathing and changing station includes a tub member for holding at least one of a predetermined amount of water, an infant, and a combination thereof. Such tub member is manufactured from a first predetermined material and has a first predetermined size and a first predetermined shape. A plurality of leg members each have a first end and a second end and each of such first ends of such plurality of leg members are operably connected to an outer surface of such tub member at predetermined locations thereon for supporting such tub member at a predetermined height. Such leg members are manufactured from a second predetermined material and have a second predetermined size and a second predetermined shape.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.