Abstract: A system and method for performing persistent comply to connect (C2C) for establishing a connection to a network is provided. The method includes receiving, at a secure access (SA) server from an endpoint device, a request to access a network, and continuously collecting, by a secure endpoint (SE) agent, data from the endpoint device. Based on the continuous collection, determining a compliance status of the endpoint device, and automatically enforcing, by an SA server, one or more policy actions based on real-time compliance data of the endpoint device to force the endpoint device into compliance. The method further includes continuously monitoring, after the endpoint device has been granted access to the network, the compliance status of the endpoint device for a change event, and automatically enforcing a policy action to resolve a change in the compliance status.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

Abstract: According to one general aspect, an apparatus may include a processor coupled with a memory controller via a first path and a second path. The first path may traverse a coherent interconnect that couples the memory controller with a plurality of processors, including the processor. The second path may bypass the coherent interconnect and has a lower latency than the first path. The processor may be configured to send a memory access request to the memory controller and wherein the memory access request includes a path request to employ either the first path or the second path. The apparatus may include the memory controller configured to fulfill the memory access request and, based at least in part upon the path request, send at least part of the results of the memory access to the processor via either the first path or the second path.

Abstract: A method includes: receiving a coherent request from a requester; looking up a state array of a snoop filter table corresponding to an index identified by the coherent request; determining state information corresponding to the coherent request; and determining to access one or more address tag arrays of the snoop filter table based on one or more of the state information, the requester, and a type of the coherent request.

Abstract: A method includes: receiving a coherent request from a requester; looking up a state array of a snoop filter table corresponding to an index identified by the coherent request; determining state information corresponding to the coherent request; and determining to access one or more address tag arrays of the snoop filter table based on one or more of the state information, the requester, and a type of the coherent request.

Abstract: A method to provide a user an informational tour of a location includes emitting a position signal from a wireless device at a position along the informational tour, detecting the position signal with an electronic device, and outputting information based upon the position signal with the electronic device.

Abstract: A portable foldable infant bathing and changing station includes a tub member for holding at least one of a predetermined amount of water, an infant, and a combination thereof. Such tub member is manufactured from a first predetermined material and has a first predetermined size and a first predetermined shape. A plurality of leg members each have a first end and a second end and each of such first ends of such plurality of leg members are operably connected to an outer surface of such tub member at predetermined locations thereon for supporting such tub member at a predetermined height. Such leg members are manufactured from a second predetermined material and have a second predetermined size and a second predetermined shape.

Abstract: Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component.

Abstract: The present invention generally provides a sputtering apparatus and method in which a sputtering target has a plurality of target sections bonded to a common backing plate. Each segment can be bonded to the common backing plate using a different bonding material. One target segment can be bonded to the backing plate using electrically conductive bonding material while another section is bonded to the backing plate using electrically insulating bonding material. Additionally, each different target section can be separately biased.

Abstract: The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.

Abstract: The invention provides antiandrogenic compositions and methods of use. The general methods deliver an antiandrogen to a host determined to be in need thereof by contacting the host with an effective amount of an antiandrogenic, optionally substituted 3,3?-diindolylmethane (DIM); and detecting a resultant antiandrogenic response in the host. The method may further comprise, prior to the contacting step, determining that the host is in need of the antiandrogen.

Abstract: A power supply for a rechargeable battery in a portable computer system is disclosed which adjusts the level of charging current depending upon the current drawn by the portable computer system. The power supply includes an AC adapter which supplies input current for operating the computer system and for charging the battery. Sensors are connected to the AC adapter, the battery, and an output of the power supply to detect the level of input current from the AC adapter, the level of charging current supplied to the battery, and the output voltage level of the power supply. A controller is connected to each of the sensors and monitors the input current level, the charging current level, and the output voltage level. The controller generates a control signal which indicates whether any one of the levels has exceeded a respective predetermined maximum value.