Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.

Abstract: Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.

Abstract: High absorbency lyocell fibers are obtainable by hydrothermal treatment. The fibers can be treated with water at temperatures of at least 60° C. to provide lyocell fibers that can be formed into a random fibrous plug having a mass of 2 g, a density of 0.4 g/cm3, and a diameter of 25 mm which has a GAT Absorbency (at 15 min.) of at least about 3.7 g/g.

Abstract: High absorbency lyocell fibers are obtainable by hydrothermal treatment. The fibers can be treated with water at temperatures of at least about 60° C. to provide lyocell fibers that can be formed into a random fibrous plug having a mass of 2 g, a density of 0.4 g/cm3, and a diameter of 25 mm which has a GAT Absorbency (at 15 min.) of at least about 3.7 g/g.

Abstract: The invention relates to a tire for heavy vehicle of the agricultural or construction type, comprising a carcass reinforcement radially surmounted by a crown reinforcement, itself topped radially by a tread, said tread being joined to two beads by means of two sidewalls. According to the invention, the tire is such that the form ratio H/S is less than 0.75 and the ratio of the width of the tread A to the height of deflection B of the crown is greater than 17.

Abstract: The invention relates to a tire for heavy vehicle of the agricultural or construction type, comprising a carcass reinforcement radially surmounted by a crown reinforcement, itself topped radially by a tread, said tread being joined to two beads by means of two sidewalls. According to the invention, the tire is such that the form ratio H/S is less than 0.75 and the ratio of the width of the tread A to the height of deflection B of the crown is greater than 17.

Abstract: An absorbent article including an absorbent structure is disclosed. The absorbent structure has an absorbent core and a plurality of discrete entities deposited on the absorbent core, wherein the combination of absorbent core and discrete entities form a body facing surface of the absorbent article.

Abstract: High absorbency lyocell fibers are obtainable by hydrothermal treatment. The fibers can be treated with water at temperature of at least about 60° C. to provide lyocell fibers that can be formed into a random fibrous plug having a mass of 2 g, a density of 4 g/cm3, and a diameter of 25 mm which has a GAT Absorbency (at 15 min.) of at least about 3.7 g/g.

Abstract: An absorbent device having an absorbent structure substantially free of modified cellulosic fibers having carboxyalkyl substituted cellulosic regions and having at least one surface substantially covered by an outer layer, and an outer portion comprised of modified cellulosic fibers having modified cellulosic fibers having carboxyalkyl substituted cellulosic regions, wherein the outer portion forms a layer on the at least one surface of the absorbent portion.