Abstract: Systems design and methods are provided for maintaining the memory array stability while reducing power consumption in the form of leakage current in a memory array. One embodiment discloses a memory array system, which comprises a plurality of memory cells, a monitor cell array, a controller, and voltage regulator circuits. The controller receives information from the monitor cell array, determines the state of stability, and adjusts the voltage regulators accordingly to ensure the memory array stability and minimizes leakage.

Abstract: Systems and methods are provided for reducing leakage current and maintaining high performance in a static random access memory (SRAM). One embodiment discloses a memory array system operative to store data bits in individually addressable rows and columns. The memory array system comprises a plurality of memory blocks, each of the plurality of memory blocks having a plurality of memory rows and a row peripheral circuit operative to switch a memory block from a retention mode to an activation mode in response to an addressing of a memory row within the memory block.

Abstract: An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical grouping of memory cells, configured to bias a subset of the set based on a memory address associated therewith. In another embodiment, a method includes receiving a memory address associated with the hierarchical grouping of memory cells and biasing a subset of the hierarchical grouping of memory cells based on the memory address.

Abstract: An SRAM device a method of placing a portion of memory cells of an SRAM device in an active mode. In one embodiment, the SRAM device includes (1) a set of memory cells and (2) biasing circuitry, coupled to the set, configured to bias a subset of the set based on a memory address associated therewith.

Abstract: In an equalizer filter unit, the filter is divided into a plurality of sequential segments. While all the components of the equalizer unit multiply data signal groups by the a coefficient signal group, in only one segment are the coefficient signal groups updated. The data and the coefficient signal groups are periodically transferred to the next sequential filter segment while the filter segments are reconfigured in the original sequential order. In this manner, the each data signal group interacts with a coefficient signal group in the original sequential order. Because the coefficients are updated in only one of the filter segments, the amount of apparatus required for processing signal groups is reduced.

Abstract: A signal transfer system (10) includes a driver (12) coupled to a receiver (14) using a signal line (16). The driver (12) drives the signal line (16) from an intermediate voltage (22) to a selected first or second voltage to indicate a transition of the input (18). The use of the intermediate voltage (22) on the signal line (16) reduces the effective switching capacitance, which reduces power dissipated by the signal transfer system (10).

Abstract: An integrated circuit device having a memory array (50) with segmented bit lines and a method of operation are disclosed. A sub array (52) of the memory array (50) can be operated as a multiple port sub array. A bit line of the sub array (52) is separated into bit line segments by disconnecting the bit line segments (54) from one another. A first bank of sense amplifiers (58) is connected to a first bit line segment (54) of the sub array (52), and a second bank of sense amplifiers (58) is connected to a second bit line segment (54) of the sub array (52). A first operation is performed to the first bit line segment (54) using the first bank of sense amplifiers (58), and a second operation is concurrently performed to the second bit line segment (54) using the second bank of sense amplifiers (58).

Abstract: A semiconductor static random access memory (RAM) array (10) is disclosed. The static RAM array (10) includes a plurality of memory cells (12), where each memory cell (12) is coupled to a write enable switch (34). The write enable switch (34) responsive to a write enable signal (36) is coupled between each memory cell (12) and a voltage source (27) or a voltage ground (29). The write enable switch (34) can disconnect each memory cell (12) from either the voltage source (27) or the voltage ground (29) responsive to the write enable signal.

Abstract: An array of individual elements (10) having reduced control circuitry as compared to existing devices. Sets of elements (11) share a memory cell (12), such that each memory cell (12) has the same fanout as other memory cells (12). Each element (11) in a set is switched to an on or off state via a reset line (13) that is separate from that of the other elements (11) in that set. Data is loaded in split bit-frames during a set time period, such that each split bit-frame contains only the data for elements (11) on one reset line (13). Thus, the same memory cell (12) can be used to deliver data to all elements (11) in its fanout because only one element (11) in the fanout is switched at a time.

Abstract: A memory array architecture is disclosed which funnels data through a series of sets of input/output data lines. Additionally, the invention allows a variable number of sense amplifiers to be used with a single local differential amplifier, thereby permitting high speed sensing.

Abstract: The low-power two-stage data output buffer (20,70) includes a two-stage switching circuit (50, 72) that drives an n-channel pull-up transistor (24) in two stages, thus only using current from the pumped high voltage supply during the second stage of the operation. The two-stage switching circuit (50, 72) first drives the pull-up transistor (24) with the supply voltage, V.sub.DD, then drives it with the pumped high voltage supply, V.sub.PP. A feedback circuit, coupled between the output node (28) and the two-stage switching circuit (50, 72), generates a path from the high voltage supply, V.sub.PP, to the n-channel pull-up transistor (24) in response to the supply voltage level appearing on the output node (28), and blocks the path from the high voltage supply, V.sub.PP, to the supply voltage.

Abstract: A combination dynamic random access memory (DRAM) and static random access memory (SRAM) (150) array, includes a plurality of DRAM sense amplifiers (82, 84), each coupled to at least one DRAM bitline (86), with a plurality of DRAM memory cells selectively coupled to each of the bitlines (86). The sense amplifiers (82, 84) are organized into groups, with each group of sense amplifiers (82, 84), selectively coupled to respective true and complement I/O lines (102, 104). For each pair of the true and complement I/O lines (102, 104), an SRAM latch (150) is coupled to the pair.

Abstract: A differential amplifier includes first and second amplifying circuits for providing a differential output. Circuitry is provided to prevent forward-biasing of the transistors of the differential amplifiers.

Abstract: A BiCMOS bandgap reference voltage circuit is disclosed wherein substantial independence from a specified variation in supply voltage is accomplished through establishing a feedback loop between the output of the circuit and the input of the circuit such that the input is a function of the output.

Abstract: A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resistive circuitry which allow bootstrapped voltages.

Abstract: A high-speed level shifter converts ECL logic levels to CMOS logic levels for use in an ECL BiCMOS circuit. A CMOS inverter (34) is connected to the output of an emitter coupled pair through a resistor (36). A current reference circuit ensures that the voltage drop across the resistor (36) is such to shift the ECL logic level to the trip point of the CMOS buffer.

Abstract: A multiple input differential sense amplifier including a pair of signal inputs and comprising a bank of n-channel MOS transistors for receiving said multiple inputs for connection to one of said signal inputs. The other of said signal inputs can be provided with a fixed bias input, or a complementary input from a complementary bank of n-channel MOS transistors.

Abstract: A high speed CMOS NOR gate employs a pair of cross-coupled inverters and a dual set of N-channel pulldown transistors (202, 203) at each of the nodes between the two inverters, together with small pullup transistor (205) on the output terminal that is permanently energized and a switchable large pullup transistor (220) that is a link between the second inverter output and the first inverter input.

Abstract: CMOS memory arrangement including a circuit for setting the dataline voltage at a predetermined bias level, the circuit comprising four MOS transistors, the first, second and third and the first and fourth thereof being connected in respective series from VCC to ground, the gates of the first and second transistors being connected to ground, the bias level being established between the second and third transistors with the gate of the third transistor being connected to the node therebetween.

Abstract: A synchronizing buffer arrangement for a CMOS memory with output drive transistors receiving one of a pair of input data signals, and being subject to the pull-up and pull-down support of the other of said data signals.