Patents by Inventor Hieu Van Tran

Hieu Van Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12279428
    Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: April 15, 2025
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
  • Publication number: 20250104783
    Abstract: In one example, a method comprises determining a logarithmic slope factor for a selected analog non-volatile memory cell in an array of analog non-volatile memory cells while the selected analog non-volatile memory cell is operating in a sub-threshold region; storing the logarithmic slope factor; determining a linear slope factor for the selected analog non-volatile memory cell while the selected analog non-volatile memory cell is operating in a linear region; storing the linear slope factor; and utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected analog non-volatile memory cell to a target current.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Hieu Van Tran, Thuan VU, Stephen TRINH, Stanley HONG, Anh LY, Steven LEMKE, Nha NGUYEN, Vipin TIWARI, Nhan DO
  • Publication number: 20250085884
    Abstract: A method of operating memory cells includes programming memory cells at a first temperature to different program states associated with first read current values confirmed by using nominal read conditions. Modified read conditions are determined such that a second read current for the one memory cells at a second temperature is approximately equal to the first read current value for the one memory cell. A read operation is performed on the memory cells at the second temperature using the modified read conditions to determine respective third read current values. Error read current values are determined as respective differences between the first and third read current values. Upper and lower program states are assigned to respective desired program states, with read currents that correspond approximately to respective determined error read current values, and are separated approximately by a respective target read current value associated with the respective desired program state.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Inventors: Gilles Festes, Steven Lemke, Louisa Schneider, Henry A. Om'mani, Hieu Van Tran
  • Patent number: 12248870
    Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: March 11, 2025
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
  • Patent number: 12249368
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.
    Type: Grant
    Filed: April 24, 2024
    Date of Patent: March 11, 2025
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 12243587
    Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: March 4, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stephen Trinh, Stanley Hong, Thuan Vu, Anh Ly, Fan Luo
  • Publication number: 20250068900
    Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns, a first set of columns storing W+ weights and a second set of columns storing W? weights; and an output circuit to receive a first current from a respective column in the first set of columns and a second current from a respective column in the second set of columns and to generate a first voltage and a second voltage, the output circuit comprising a first current-to-voltage converter comprising a first integration capacitor to provide the first voltage equal to an initial voltage minus a first discharge value due to the first current, and a second current-to-voltage converter comprising a second integration capacitor to provide the second voltage equal to the initial voltage minus a second discharge value due to the second current.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 27, 2025
    Inventors: HIEU VAN TRAN, ANDREW KUNIL CHOE, HOA VU
  • Publication number: 20250068861
    Abstract: Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2m different analog voltages to an associated row in the array.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 27, 2025
    Inventors: Hieu Van Tran, Stephen Trinh, Hoa Vu, Stanley Hong, Thuan Vu
  • Patent number: 12237011
    Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 25, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
  • Patent number: 12229004
    Abstract: Numerous examples are disclosed of an improved grouping and error correction system for non-volatile memory cells. In one example, a system comprises a memory array comprising non-volatile memory cells arranged into rows and columns, wherein a non-volatile memory cell of the memory array stores a first bit of a first data grouping and a second bit of a second data grouping, and wherein the first grouping is backed by a first ECC block and the second grouping is backed by a second ECC block.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: February 18, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventor: Hieu Van Tran
  • Patent number: 12230319
    Abstract: Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed. In some embodiments, a method is performed to determine in real-time a bias value to apply to one or more memory cells in a neural network. In other embodiments, a bias voltage is determined from a lookup table and is applied to a terminal of a memory cell during a read operation.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: February 18, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventor: Hieu Van Tran
  • Patent number: 12217165
    Abstract: Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed. In some embodiments, concurrent operations occur among different banks of memory. In other embodiments, concurrent operations occur among different blocks of memory, where each block comprises two or more banks of memory. The embodiments substantially reduce the timing overhead for weight writing and verifying operations in analog neural memory systems.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: February 4, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventor: Hieu Van Tran
  • Patent number: 12205655
    Abstract: In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: January 21, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Patent number: 12198043
    Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: January 14, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
  • Patent number: 12200926
    Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: January 14, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 12176039
    Abstract: In one example, a method comprises determining a program resolution current value; and setting levels for a programming operation of a plurality of non-volatile memory cells in a neural network array such that a delta current between levels of each pair of adjacent cells in the plurality is a multiple of the program resolution current value.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: December 24, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stanley Hong, Stephen Trinh, Thuan Vu, Steven Lemke, Vipin Tiwari, Nhan Do
  • Patent number: 12131786
    Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: October 29, 2024
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Louisa Schneider, Xian Liu, Steven Lemke, Parviz Ghazavi, Jinho Kim, Henry A. Om'Mani, Hieu Van Tran, Nhan Do
  • Patent number: 12124944
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: October 22, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Mark Reiten
  • Publication number: 20240347111
    Abstract: In one example, a circuit for comparing current drawn by a selected memory cell for a vector-matrix-multiplier with current drawn by a reference matrix comprises a first circuit comprising a first PMOS transistor coupled to a first NMOS transistor coupled to the selected memory cell; and a second circuit comprising a second PMOS transistor coupled to a second NMOS transistor coupled to the reference matrix; wherein a node between the second PMOS transistor and the second NMOS transistor outputs a current indicative of a value stored in the selected memory cell.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 17, 2024
    Inventors: Hieu Van Tran, Vipin Tiawari, Nhan Do, Mark Reiten
  • Publication number: 20240339136
    Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m?2u, n?2v, and p?2t.
    Type: Application
    Filed: June 6, 2023
    Publication date: October 10, 2024
    Inventors: Kha Nguyen, Anh Ly, Hieu Van Tran, Hien Pham, Henry Tran