Patents by Inventor Hieu Van Tran

Hieu Van Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low voltage level shifter for integrated circuit
    Patent number: 11038495
    Abstract: An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75 V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: June 15, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Ryan Mei, Xiaozhou Qian, Hieu Van Tran, Claire Zhu
  • OUTPUT CIRCUITS FOR AN ANALOG NEURAL MEMORY SYSTEM FOR DEEP LEARNING NEURAL NETWORK
    Publication number: 20210174185
    Abstract: Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network. In one embodiment, an adaptable neuron circuit receives output current from a neuron and converts it into a voltage. In another embodiment, a current sample and hold circuit samples an input current and generates an output current. In another embodiment, a voltage sample and hold circuit samples an input voltage and generates an output voltage.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
  • VIRTUAL GROUND NON-VOLATILE MEMORY ARRAY
    Publication number: 20210175240
    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
  • Power line compensation for flash memory sense amplifiers
    Patent number: 11031050
    Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 8, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Hieu Van Tran
  • Low Voltage Level Shifter For Integrated Circuit
    Publication number: 20210167762
    Abstract: An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.
    Type: Application
    Filed: April 2, 2020
    Publication date: June 3, 2021
    Inventors: Ryan Mei, XIAOZHOU QIAN, HIEU VAN TRAN, CLAIRE ZHU
  • Flash memory cell and associated high voltage row decoder
    Patent number: 11011240
    Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 18, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • VERIFYING OR READING A CELL IN AN ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210142854
    Abstract: Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Mark Reiten
  • Precise Programming Method And Apparatus For Analog Neural Memory In An Artificial Neural Network
    Publication number: 20210142156
    Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 13, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Memory cell with floating gate, coupling gate and erase gate, and method of making same
    Patent number: 10998325
    Abstract: A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 4, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Catherine Decobert, Hieu Van Tran, Nhan Do
  • INPUT AND DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210118894
    Abstract: Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Toan Le, Nghia Le, Hien Pham
  • Four Gate, Split-Gate Flash Memory Array With Byte Erase Operation
    Publication number: 20210110873
    Abstract: A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.
    Type: Application
    Filed: February 6, 2020
    Publication date: April 15, 2021
    Inventors: Hsuan Liang, Man Tang Wu, Jeng-Wei Yang, Hieu Van Tran, Lihsin Chang, Nhan Do
  • INPUT AND DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210098477
    Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Hieu Van Tran, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
  • TEMPERATURE COMPENSATION IN AN ANALOG MEMORY ARRAY BY CHANGING A THRESHOLD VOLTAGE OF A SELECTED MEMORY CELL IN THE ARRAY
    Publication number: 20210090654
    Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 25, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Nhan Do, Vipin Tiwari, Mark Reiten
  • PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20210089875
    Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 25, 2021
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Configurable analog neural memory system for deep learning neural network
    Patent number: 10956814
    Abstract: Numerous embodiments are disclosed for a configurable hardware system for use in an analog neural memory system for a deep learning neural network. The components within the configurable hardware system that are configurable can include vector-by-matrix multiplication arrays, summer circuits, activation circuits, inputs, reference devices, neurons, and testing circuits. These devices can be configured to provide various layers or vector-by-matrix multiplication arrays of various sizes, such that the same hardware can be used in analog neural memory systems with different requirements.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 23, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Mark Reiten, Nhan Do
  • Programming Circuit and Method For Flash Memory Array
    Publication number: 20210082516
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Current compensation block and method for programming analog neural memory in deep learning artificial neural network
    Patent number: 10943661
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: March 9, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • CHARGE PUMP FOR USE IN NON-VOLATILE FLASH MEMORY DEVICES
    Publication number: 20210035643
    Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Kha Nguyen, Hien Pham, Stanley Hong, Stephen T. Trinh
  • Method and apparatus for programming analog neural memory in a deep learning artificial neural network
    Patent number: 10910061
    Abstract: Numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 2, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Mark Reiten
  • Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
    Publication number: 20210019608
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 21, 2021
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do