Abstract: A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.

Abstract: A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.

Abstract: A disk controller which includes a plurality of interfaces to host computers or disk devices, each interface having a processor, a memory unit coupled to the interfaces in a one-to-one ratio by respective access paths, the memory unit having a memory in which information is stored, and a common bus coupling to the processors included in the interfaces. Each processor of each interface transmits broadcast data to all of the processors of the interfaces, except its own, by way of the common bus.

Abstract: The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

Abstract: A disk array controller installed with a plurality of interfaces with the host computer or disk device, duplicated shared memories connected in a ratio of one to one between each interface and respective access path, a selector connected to the plurality of interfaces, and a cache memory connected to said selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor for the plurality of interfaces performs dual writing in the duplicated shared memories.

Abstract: A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.

Abstract: The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

Abstract: A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.