Patents by Inventor Hikaru Ikegami
Hikaru Ikegami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9613922Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: December 24, 2014Date of Patent: April 4, 2017Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20150108639Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: December 24, 2014Publication date: April 23, 2015Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 8952527Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: January 7, 2014Date of Patent: February 10, 2015Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20140117541Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: January 7, 2014Publication date: May 1, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 8653655Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: August 6, 2013Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20130320571Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: August 6, 2013Publication date: December 5, 2013Applicant: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 8524534Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: June 26, 2012Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20120264240Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Inventors: Yoshiyuki KADO, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kirkuchi
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Patent number: 8278147Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: September 23, 2009Date of Patent: October 2, 2012Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20110171780Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 7859095Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: April 7, 2009Date of Patent: December 28, 2010Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 7745915Abstract: A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device are determined in such a manner that wirings for data and a data strobe system (RTdq/dqs) become shorter than wirings for a command/address system (RTcmd/add). The wirings for the data and data strobe system (RTdq/dqs) are laid down using an area defined between the semiconductor memory devices. The wirings for the command/address system (RTcmd/add) bypass the side of the mounting board.Type: GrantFiled: February 24, 2006Date of Patent: June 29, 2010Assignee: Renesas Technology Corp.Inventors: Motoo Suwa, Hikaru Ikegami, Takafumi Betsui
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Publication number: 20100015760Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: September 23, 2009Publication date: January 21, 2010Inventors: Yoshiyuki KADO, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20090189268Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: April 7, 2009Publication date: July 30, 2009Inventors: Yoshiyuki KADO, Takahiro Naito, Hikaru Ikegami, Takafumi Kikuchi, Toshihiko Sato
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Patent number: 7531441Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: April 7, 2006Date of Patent: May 12, 2009Assignee: Renesas Technology Corp.Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20060192282Abstract: A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device are determined in such a manner that wirings for data and a data strobe system (RTdq/dqs) become shorter than wirings for a command/address system (RTcmd/add). The wirings for the data and data strobe system (RTdq/dqs) are laid down using an area defined between the semiconductor memory devices. The wirings for the command/address system (RTcmd/add) bypass the side of the mounting board.Type: ApplicationFiled: February 24, 2006Publication date: August 31, 2006Inventors: Motoo Suwa, Hikaru Ikegami, Takafumi Betsui
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Publication number: 20060189031Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: April 7, 2006Publication date: August 24, 2006Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 7042073Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: April 5, 2002Date of Patent: May 9, 2006Assignee: Renesas Technology Corp.Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20050169033Abstract: A high speed operating circuit such as a data processor chip and memory chips constituting an electronic circuit is mounted to a multilayer wiring substrate in the state of a bare chip, and is set to a multichip module. This multichip module is mounted to a wiring substrate constituting the electronic circuit. In the multichip module, buffer circuits are inserted into a module internal bus commonly connected to the data processor chip and the memory chips. The buffer circuits are set to an address output buffer, a control signal output buffer and a data input/output buffer set to a high impedance state in accordance with an operating selection of the memory chips. When high frequency noise resisting characteristics are strengthened by the multilayer wiring substrate and the data processor chip gets access to the memory chips, an external noise tends to flow into a memory through the module internal bus connected to the data processor chip and the memory chips.Type: ApplicationFiled: April 1, 2005Publication date: August 4, 2005Inventors: Norihiko Sugita, Takafumi Kikuchi, Koichi Miyashita, Hikaru Ikegami