Patents by Inventor Hikaru Tamura

Hikaru Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374023
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 28, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Publication number: 20220144570
    Abstract: A sheet conveying device includes a tray, a device body having a conveying route of a sheet and supporting the tray, a side guide supported by the tray to be movable in a first direction intersecting with a conveying direction of the sheet and contacting an end portion in the first direction of the sheet placed on the tray, a cover rotatable with respect to the device body and covering the conveying route, and a lock lever locking the cover to the device body and provided in a position overlapping the side guide in a second direction intersecting with the conveying direction and the first direction. The lock lever is rotatable between a lock position where the cover is locked and a release position where the cover is released. The side guide includes a first notched portion facing a rotation track of the lock lever with a gap.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 12, 2022
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Akinari ISHIBE, Hideaki YOSHIMUNE, Hikaru TAMURA
  • Patent number: 11264415
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: March 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Patent number: 11239268
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Publication number: 20220020793
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Patent number: 11205820
    Abstract: In an upper cell unit (2146) and a lower cell unit (2147) comprising five battery cells, positive electrode terminals (2162, 2172) are set apart and aligned vertically, and negative electrode terminals (2167, 2177) are set apart and aligned vertically. When an electrical device body is rated at 36V, device-side terminals are in contact only at the upper terminals (2162, 2167), and short circuiting of the lower terminals (2172, 2177) is effected using a short bar 2059. When the electrical device body is rated at 18V, the upper and lower terminals (2162 and 2172, 2167 and 2177) are simultaneously made to contact the device-side terminals, and the upper cell unit (2146) and the lower cell unit (2147) assume a parallel connected state. Thus, it is possible to automatically switch the output voltage when a battery pack is mounted according to the difference in terminal shape on the electrical device body side.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 21, 2021
    Assignee: Koki Holdings Co., Ltd.
    Inventors: Hiroyuki Hanawa, Tomomasa Nishikawa, Shota Kanno, Toshio Mizoguchi, Yasushi Nakano, Kazuhiko Funabashi, Takuya Teranishi, Naoto Wakatabe, Shinji Watanabe, Junpei Sato, Hikaru Tamura, Nobuhiro Takano, Osamu Kawanobe, Hayato Yamaguchi, Akira Matsushita, Masaru Hirano, Takuhiro Murakami, Masayuki Ogura, Yusuke Funabiki, Junichi Toukairin, Shota Takeuchi
  • Patent number: 11139327
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 5, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Publication number: 20210300093
    Abstract: There is provided an ink-jet printer, including: a tray; a recording section including a carriage and a head; a reservoir; a tube; a platen; a first guide member arranged at a front side of the recording section in a front-rear direction and having a first curved surface configured to guide a first surface of the sheet; a discharge section configured to discharge the sheet from a rear side toward the front side in the front-rear direction, the discharge section being arranged at the rear side of the recording section; a second guide member arranged at the rear side of the recording section and having a second curved surface configured to guide the first surface of the sheet; and a loading section configured to load the sheet discharged from the discharge section thereon. The loading section includes an inclined portion at the rear side of the recording section, the inclined portion being inclined upward toward the front side of the discharge section.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 30, 2021
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Hikaru TAMURA, Tsuyoshi KUWAYAMA, Fumio NAKAZAWA, Yoshinori OSAKABE, Hirotaka AOKI
  • Patent number: 11104534
    Abstract: A sheet conveyer, including a first guide with a guide surface, a second guide arranged on a side of the guide surface toward one end in a widthwise direction, a first roller arranged upstream in a conveying direction from the second guide to rotate about a first axis extending in parallel with the widthwise direction, a second roller arranged downstream in the conveying direction from the first roller to rotate about a second axis inclined with respect to the widthwise direction, and a third roller arranged downstream in the conveying direction from the second roller at a position on a side of the guide surface toward the other end in the widthwise direction outside a widthwise length of the sheet, is provided. The third roller is configured to rotate about a third axis inclined with respect to the widthwise direction.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 31, 2021
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Shoichiro Nishimura, Hikaru Tamura, Kazuya Kamikawa, Yuichiro Ichinose
  • Publication number: 20210225909
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA
  • Publication number: 20210225910
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA
  • Patent number: 10964393
    Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: March 30, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hikaru Tamura
  • Publication number: 20210082976
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Application
    Filed: June 15, 2020
    Publication date: March 18, 2021
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA
  • Patent number: 10950297
    Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Hikaru Tamura
  • Publication number: 20210074734
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Application
    Filed: October 29, 2020
    Publication date: March 11, 2021
    Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
  • Publication number: 20200381056
    Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventor: Hikaru TAMURA
  • Patent number: 10825836
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 3, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Publication number: 20200316744
    Abstract: A wire electrical discharge machine acquires measured dimensions of a test workpiece that has been machined with a wire electrode inclined at a given angle with respect to a running direction in which the wire electrode runs; and calculates, based on the measured dimensions, first actual information indicating an actual holding position at which the wire electrode is actually held at a first die guide for guiding the wire electrode to a workpiece, and second actual information indicating an actual holding position at which the wire electrode is actually held at a second die guide for guiding the wire electrode sent from the workpiece, and, when necessary, the wire electrical discharge machine rewrites first information and second information stored in a storage unit to the calculated first actual information and second actual information.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 8, 2020
    Inventors: Daiki WATANABE, Ryousuke SUGANUMA, Riho KUBOTA, Hikaru TAMURA
  • Patent number: 10685992
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Publication number: 20200168635
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Application
    Filed: October 18, 2019
    Publication date: May 28, 2020
    Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE