Patents by Inventor Hikaru Tamura

Hikaru Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055674
    Abstract: An electrical device body connectable to a battery pack, includes a drive part, and a terminal part. The terminal part having a positive input terminal electrically connected to the drive part, a negative input terminal electrically connected to the drive part, and a short circuit element having a first terminal part, a second terminal part, and a connection part connecting the first terminal part and the second terminal part, wherein the positive input terminal and the negative input terminal are disposed on an upper side of the terminal part and the short circuit element is disposed on a lower side of the terminal part in an upper-lower direction, the positive input terminal and the negative input terminal being apart from each other in a left-right direction crossing the upper-lower direction.
    Type: Application
    Filed: September 27, 2023
    Publication date: February 15, 2024
    Applicant: Koki Holdings Co., Ltd.
    Inventors: Tomomasa NISHIKAWA, Takuya Teranishi, Naoto Wakatabe, Akira Matsushita, Masaru Hirano, Osamu Kawanobe, Nobuhiro TAKANO, Shinji Watanabe, Hiroyuki HANAWA, Takuhiro Murakami, Shota Kanno, Junpei SATO, Hikaru Tamura, Hayato Yamaguchi, Toshio Mizoguchi, Yasushi NAKANO, Kazuhiko FUNABASHI, Masayuki Ogura, Yusuke FUNABIKI, Junichi TOUKAIRIN, Shota TAKEUCHI
  • Publication number: 20240047912
    Abstract: A connector system having a first connector and a second connector. The first connector is mounted to a substrate and includes a housing and a first shell. The first shell has solder hold down posts which extend from a circuit board mounting surface of the first connector. Securing openings are provided in side walls of the first shell. The second connector includes a daughterboard and a second shell. The second shell has side plates, resilient latching projections are formed from mating connector alignment portions positioned on the side plates proximate a connector receiving surface of the second connector. The resilient latching projections of the second connector cooperate with the securing openings of the first connector to secure the second connector to the first connector. The first connector is secured to the substrate by soldering the solder hold down posts to the substrate.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Applicants: TE Connectivity Solutions GmbH, Tyco Electronics Japan G.K.
    Inventors: Jevon CORBAN, Tatsuki WATANABE, Hikaru TAMURA, Chihiro HIKAGE
  • Publication number: 20240006424
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Application
    Filed: August 10, 2023
    Publication date: January 4, 2024
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA
  • Patent number: 11837741
    Abstract: The electrical apparatus, in which a series connection state and a parallel connection state of an upper cell unit including five battery cells and a lower cell unit can be automatically switched by means of a difference in a terminal shape on the electrical apparatus body side, has a terminal holder and holds apparatus side terminals. The terminal holder, which establishes an electrically connected state with the connection terminals of the battery pack, is provided with two parallel protruding parts that extend in the forward-backward direction, and second rail grooves fitted to the protruding parts on the electrical apparatus side. Due to the fitting, relative movement of the terminal holder and the battery pack in the vertical direction can be suppressed, and wear on the apparatus side terminals can be greatly suppressed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 5, 2023
    Assignee: Koki Holdings Co., Ltd.
    Inventors: Takuhiro Murakami, Tomomasa Nishikawa, Shinji Watanabe, Junpei Sato, Hikaru Tamura, Shota Kanno, Toshio Mizoguchi, Yasushi Nakano, Hiroyuki Hanawa, Kazuhiko Funabashi, Masayuki Ogura, Takuya Teranishi, Junichi Toukairin, Shota Takeuchi, Yusuke Funabiki
  • Patent number: 11824169
    Abstract: A battery pack houses first and second cell units that are composed of a plurality of cells, and has a positive electrode power source terminal and a negative electrode power source terminal. This battery pack is provided with a series connector capable of connecting, in series, the first and second cell units and a parallel connector capable of connecting, in parallel, the first and second cell units, and is capable of switching between a parallel connection voltage and a series connection voltage. In the case of attachment to the high voltage electrical device body, the series connector becomes conductive and the parallel connector pair is cut off by the action of the series/parallel switching terminal. In the case of attachment to a low voltage electrical device body, the state is returned to an initial state, the series connector is cut off, and the parallel connector pair becomes conductive.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: November 21, 2023
    Assignee: Koki Holdings Co., Ltd.
    Inventors: Tomomasa Nishikawa, Takuya Teranishi, Naoto Wakatabe, Akira Matsushita, Masaru Hirano, Osamu Kawanobe, Nobuhiro Takano, Shinji Watanabe, Hiroyuki Hanawa, Takuhiro Murakami, Shota Kanno, Junpei Sato, Hikaru Tamura, Hayato Yamaguchi, Toshio Mizoguchi, Yasushi Nakano, Kazuhiko Funabashi, Masayuki Ogura, Yusuke Funabiki, Junichi Toukairin, Shota Takeuchi
  • Publication number: 20230352502
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 2, 2023
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Publication number: 20230271432
    Abstract: An image recording apparatus includes a housing in which a conveyance path is formed, a feed tray insertable into and removable from the housing, configured to accommodate sheet media, and including a first accommodating portion, an image recording portion, a guide member configured to guide one of the sheet media, a stopper movable between a restriction state in which the stopper abuts against a leading end of the sheet medium to prevent the sheet medium from reaching a bank provided and a retraction state in which the stopper is separated from the leading end to allow the sheet medium to reach the guide member, when the feed tray is inserted into the housing, and a flap provided above the sheet media and movable in an up-down direction by pivoting about a given rotation axis.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 31, 2023
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Hikaru TAMURA, Nao MORIMOTO, Yuya TATEMATSU, Kengo NODA
  • Publication number: 20230271434
    Abstract: An image recording apparatus includes a first tray, a second tray overlapping the first tray in the first direction, a first roller configured to feed first sheet media in the first tray in a second direction, a second roller configured to feed second sheet media in the second tray in the second direction, a first separating member extending in a third direction intersecting both the first direction and the second direction, a second separating member extending in the third direction, and a recording unit. The second separating member is longer than the first separating member, and the second roller is positioned at the upstream side of the second tray with respect to the first roller in the second direction in a state where no sheet media are accommodated in the first tray and the second tray.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 31, 2023
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Hikaru TAMURA, Kengo NODA, Gakuro KANAZAWA, Nao MORIMOTO, Yuya TATEMATSU
  • Patent number: 11728354
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: August 15, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Patent number: 11710751
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 25, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Patent number: 11687295
    Abstract: A non-transitory computer-readable medium stores computer-readable instructions executable by a processor of an information processing device communicable with a printer configured to perform printing until a print permission amount reaches a particular threshold. The instructions are configured to, when executed by the processor, cause the information processing device to obtain a first number of sheets that indicates a remaining number of sheets printable according to consumable information, in response to receiving, via a user interface, an instruction to add an additional print permission amount, obtain a second number of sheets that indicates an additional number of sheets printable by the printer according to the additional print permission amount, determine whether the second number of sheets is more than the first number of sheets, and when determining that the second number of sheets is more than the first number of sheets, cause the user interface to provide a notification.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: June 27, 2023
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Hikaru Tamura
  • Publication number: 20220406826
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Application
    Filed: August 23, 2022
    Publication date: December 22, 2022
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA
  • Patent number: 11511383
    Abstract: A wire electrical discharge machine acquires measured dimensions of a test workpiece that has been machined with a wire electrode inclined at a given angle with respect to a running direction in which the wire electrode runs; and calculates, based on the measured dimensions, first actual information indicating an actual holding position at which the wire electrode is actually held at a first die guide for guiding the wire electrode to a workpiece, and second actual information indicating an actual holding position at which the wire electrode is actually held at a second die guide for guiding the wire electrode sent from the workpiece, and, when necessary, the wire electrical discharge machine rewrites first information and second information stored in a storage unit to the calculated first actual information and second actual information.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: November 29, 2022
    Assignee: FANUC CORPORATION
    Inventors: Daiki Watanabe, Ryousuke Suganuma, Riho Kubota, Hikaru Tamura
  • Patent number: 11488668
    Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hikaru Tamura
  • Publication number: 20220328530
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 13, 2022
    Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
  • Publication number: 20220314630
    Abstract: A base board includes a board and a controller mounted on the board. A controller is configured to receive signals outputted from a first sensor and a second sensor. A recording head, a case, the first sensor, a maintenance unit, a waste liquid container, the second sensor, and the base board are arranged in an internal space of a housing. The base board has a flat surface extending in a first horizontal direction and in a second horizontal direction. A range occupied by the base board in a vertical direction overlaps each of a range occupied by the first sensor in the vertical direction and a range occupied by the second sensor in the vertical direction. The second horizontal direction is perpendicular to the first horizontal direction. The vertical direction is perpendicular to both the first horizontal direction and the second horizontal direction.
    Type: Application
    Filed: March 17, 2022
    Publication date: October 6, 2022
    Inventors: Hideaki YOSHIMUNE, Hikaru TAMURA, Akinari ISHIBE
  • Publication number: 20220274410
    Abstract: An ink injection cylinder includes a first flow path tube and a second flow path tube extending in a longitudinal direction. The first flow path tube has a first opening on one side in the longitudinal direction, a second opening on another side in the longitudinal direction, and a first flow path formed between the first and second openings. The second flow path tube has a third opening on the one side in the longitudinal direction, a fourth opening on the other side in the longitudinal direction, and a second flow path formed between the third and fourth openings. At least one of a first virtual plane including at least a portion of an end surface of the second opening and a second virtual plane including at least a portion of an end surface of the fourth opening intersects with a plane orthogonal to the longitudinal direction.
    Type: Application
    Filed: April 29, 2022
    Publication date: September 1, 2022
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Yoshinori OSAKABE, Naoya OKAZAKI, Satoshi MIYASE, Hikaru TAMURA, Akinari ISHIBE, Fumio NAKAZAWA, Taichi SHIRONO, Tsuyoshi KUWAYAMA, Masahiro HAYASHI
  • Patent number: 11430820
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 30, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Publication number: 20220269450
    Abstract: A non-transitory computer-readable medium stores computer-readable instructions executable by a processor of an information processing device communicable with a printer configured to perform printing until a print permission amount reaches a particular threshold. The instructions are configured to, when executed by the processor, cause the information processing device to obtain a first number of sheets that indicates a remaining number of sheets printable according to consumable information, in response to receiving, via a user interface, an instruction to add an additional print permission amount, obtain a second number of sheets that indicates an additional number of sheets printable by the printer according to the additional print permission amount, determine whether the second number of sheets is more than the first number of sheets, and when determining that the second number of sheets is more than the first number of sheets, cause the user interface to provide a notification.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 25, 2022
    Inventor: Hikaru TAMURA
  • Patent number: 11374023
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 28, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe