Patents by Inventor HIKARU YOSHINO

HIKARU YOSHINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105735
    Abstract: In an array substrate, a plurality of wiring lines include a first wiring line located between a first pixel electrode and a second pixel electrode in a first direction, and a second wiring line located between a third pixel electrode and a fourth pixel electrode in the first direction. A plurality of switching elements include a first switching element and a second switching element. A plurality of common electrodes include a first common electrode overlapping the first pixel electrode, the second pixel electrode, the third pixel electrode, the first wiring line, and a first semiconductor portion, and a second common electrode overlapping the fourth pixel electrode and the second wiring line. Further, there is provided a first overlapping portion that is disposed overlapping a second semiconductor portion and has the same potential as that of any of the plurality of common electrodes.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 28, 2024
    Inventors: Hikaru YOSHINO, Shingo KAMITANI, Junichi MORINAGA
  • Patent number: 11914255
    Abstract: A wiring board includes position detection lines, position detection electrodes, a line, connection lines, and a short-circuit line. The position detection lines extend along a first direction and transmit at least position detection signals. The position detection electrodes are arranged at intervals with respect to the first direction and connected to the position detection lines. The line is disposed between the position detection electrodes that are adjacent to each other with respect to the first direction and the line extends in a second direction that crosses the first direction. The connection lines extend along the first direction and are connected to the position detection electrodes. The connection lines are arranged at intervals with respect to the second direction. The short-circuit line extends along the second direction and overlaps the line via an insulating film and is connected to the connection lines.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 27, 2024
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Junichi Morinaga, Hikaru Yoshino
  • Publication number: 20230288766
    Abstract: A display device includes an array substrate, a counter substrate, a first pixel electrode, a second pixel electrode spaced apart from the first pixel electrode in a first direction, a third pixel electrode spaced apart from the second pixel electrode in the first direction, a first wiring line positioned between the first pixel electrode and the second pixel electrode and extending in a second direction intersecting the first direction, a second pixel electrode row including the second pixel electrode and composed of a plurality of pixel electrodes aligned in the second direction, a third pixel electrode row including the third pixel electrode and composed of a plurality of pixel electrodes aligned in the second direction, a first insulating film disposed on a lower-layer side of the first wiring line, and a spacer protruding from the counter substrate toward the array substrate.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 14, 2023
    Inventors: Hikaru YOSHINO, Junichi MORINAGA
  • Publication number: 20230251530
    Abstract: A display device includes an array substrate, a counter substrate facing the array substrate at an interval therebetween, a plurality of pixels constituted by the plurality of pixel electrodes and the plurality of color filters, and a plurality of thin film transistors. The plurality of pixels include a plurality of first pixels each having the highest relative luminous efficiency, a plurality of second pixels each having the lowest relative luminous efficiency, and a plurality of third pixels each having relative luminous efficiency lower than the relative luminous efficiency of the first pixels and higher than the relative luminous efficiency of the second pixels, a plurality of spacers include a plurality of spacers having different overlapping relationships with the thin film transistors being overlapping targets.
    Type: Application
    Filed: January 11, 2023
    Publication date: August 10, 2023
    Inventors: Junichi MORINAGA, Hikaru YOSHINO
  • Publication number: 20230205016
    Abstract: A liquid crystal panel includes an array substrate, a counter substrate disposed to face the array substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate, in which the array substrate is provided with a plurality of pixel electrodes aligned at intervals in a plane of the array substrate, a common electrode disposed to overlap the plurality of pixel electrodes, an insulating film disposed on an upper layer side of the common electrode, and an alignment film disposed on an upper layer side of the insulating film, a light blocking portion and a spacer are provided in the counter substrate, the light blocking portion separating the plurality of pixel electrodes, the spacer being disposed to overlap the light blocking portion and protruding to the liquid crystal layer side from the counter substrate, the alignment film is connected to the common electrode directly or via another member through an opening provided in the insulating film, and the opening is disposed at
    Type: Application
    Filed: December 16, 2022
    Publication date: June 29, 2023
    Inventors: Junichi MORINAGA, Hikaru YOSHINO
  • Publication number: 20230112631
    Abstract: An active matrix substrate includes a substrate in which a notch or an aperture is formed, and electrodes. Each electrode includes at least either of: a capacitor forming portion that is arranged in a region other than a bypass region and overlaps with at least one of a plurality of bypass gate lines when viewed in a plan view; and an electrode layer portion that is formed in an electrode layer and that composes a bypass gate line interposed portion together with a source line layer portion formed in a source line layer in the bypass region. The electrode layer portion and the source line layer portion overlap with at least one of the bypass gate lines in the bypass region when viewed in a plan view, and at least one of the bypass gate lines is positioned between the electrode layer portion and the source line layer portion in a normal line direction of the substrate.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 13, 2023
    Inventors: Hikaru YOSHINO, Satoshi HORIUCHI, Junichi MORINAGA
  • Publication number: 20220326583
    Abstract: A wiring board includes position detection lines, position detection electrodes, a line, connection lines, and a short-circuit line. The position detection lines extend along a first direction and transmit at least position detection signals. The position detection electrodes are arranged at intervals with respect to the first direction and connected to the position detection lines. The line is disposed between the position detection electrodes that are adjacent to each other with respect to the first direction and the line extends in a second direction that crosses the first direction. The connection lines extend along the first direction and are connected to the position detection electrodes. The connection lines are arranged at intervals with respect to the second direction. The short-circuit line extends along the second direction and overlaps the line via an insulating film and is connected to the connection lines.
    Type: Application
    Filed: March 3, 2022
    Publication date: October 13, 2022
    Inventors: Junichi MORINAGA, Hikaru YOSHINO
  • Patent number: 10989948
    Abstract: A method for manufacturing an active matrix substrate including a thin film transistor for each pixel, and a first electrode and a first wiring line for touchscreen panel function includes: forming a transparent electrically conductive film on an interlayer insulating layer and within a first contact hole; forming, on a portion of the transparent electrically conductive film, an upper wiring portion to become an upper layer of the first wiring line; patterning the transparent electrically conductive film to make a pixel electrode and form a lower wiring portion to become a lower layer of the first wiring line; forming a dielectric layer covering the pixel electrode and the first wiring line and having a second contact hole through which a portion of the first wiring line is exposed; and forming a common electrode which is electrically connected to the first wiring line within the second contact hole.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 27, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hikaru Yoshino, Junichi Morinaga, Tetsuo Kikuchi, Kengo Hara
  • Patent number: 10978529
    Abstract: An active matrix substrate includes a first TFT of a peripheral circuit and a second TFT arranged in each pixel, wherein: the first TFT is a top gate or double gate TFT that includes an upper gate electrode on a portion of a first oxide semiconductor layer with a gate insulating layer interposed therebetween; the second TFT is a bottom gate TFT that includes a second lower gate electrode arranged on the substrate side of a second oxide semiconductor layer with a lower insulating layer interposed therebetween and includes no gate electrode on the second oxide semiconductor layer; the second TFT including: an island-shaped insulator layer that is arranged on a portion of the second oxide semiconductor layer so as to overlap with at least a portion of the second lower gate electrode, as seen from a direction normal to the substrate; an upper insulating layer that is arranged on the second oxide semiconductor layer and the island-shaped insulator layer; and a source electrode that is arranged on the upper insulat
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 13, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Junichi Morinaga, Hikaru Yoshino
  • Patent number: 10962824
    Abstract: A color filter substrate includes a light transmissive substrate, a light blocking layer, a light transmissive layer, and a color layer. The light blocking layer is formed on the light transmissive substrate. The light transmissive layer is formed along an edge of the light blocking layer on the light transmissive substrate. The color layer passes rays of visible light and is tinted a predefined color so that the rays passing therethrough exhibit a predefined color. The color layer includes a section disposed on a top surface of the light transmissive substrate in a blank area and an edge section extending from the section in the blank area over the light transmissive layer and a section of the light blocking layer. A thickness of a section of the light transmissive layer on a blank area side is less than a thickness of the light blocking layer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 30, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Katsuhiro Mikumo, Junichi Morinaga, Hikaru Yoshino
  • Publication number: 20200326576
    Abstract: A display panel includes: a pair of substrates provided opposite each other with a substrate-to-substrate distance between the substrates; a plurality of pixels arranged in a matrix, the pixels including pixel sections; inter-pixel-section light-blocking sections providing partitions between the pixel sections; spacers arranged, between the substrates, in locations over the inter-pixel-section light-blocking sections; and extended light-blocking sections provided so as to extend inward of the pixel sections from the inter-pixel-section light-blocking sections, wherein the spacers include: first spacers regulating the substrate-to-substrate distance; and second spacers and third spacers projecting from the substrate toward the substrate, the second spacers and third spacers having a projection length smaller than the substrate-to-substrate distance, the third spacers having a smaller footprint than do the second spacers.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 15, 2020
    Inventors: SHINGO KAMITANI, SHINGO JOHGAN, JUNICHI MORINAGA, HIKARU YOSHINO
  • Patent number: 10725326
    Abstract: An active matrix substrate includes: a TFT being disposed on each of a plurality of pixel regions and including an oxide semiconductor layer; an interlayer insulating layer covering the TFT; and a plurality of pixel electrodes, a common electrode including a plurality of common electrode subportions, and a plurality of first wiring lines which are disposed on the interlayer insulating layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 28, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hikaru Yoshino, Junichi Morinaga
  • Patent number: 10620495
    Abstract: The present invention provides a liquid crystal display device which includes: a first substrate; a second substrate; and a light-shielding member disposed between adjacent sub-pixels having different colors, the first substrate includes a second electrode provided with a slit, the slit includes a main slit extending in a first direction and a sub-slit extending in a second direction, when the light-shielding member is provided on the first substrate, the light-shielding member is widened on a side of a closer sub-slit among the sub-slits formed in the sub-pixels that have different colors and disposed on both sides of the light-shielding member, and the light-shielding member is not widened on a side of a farther sub-slit, and when the light-shielding member is provided on the second substrate, the light-shielding member is widened on the side opposite to the case of the first substrate.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Junichi Morinaga, Hikaru Yoshino, Shogo Suzuki
  • Publication number: 20200089038
    Abstract: An active matrix substrate includes: a TFT being disposed on each of a plurality of pixel regions and including an oxide semiconductor layer; an interlayer insulating layer covering the TFT; and a plurality of pixel electrodes, a common electrode including a plurality of common electrode subportions, and a plurality of first wiring lines which are disposed on the interlayer insulating layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 19, 2020
    Inventors: Hikaru YOSHINO, Junichi MORINAGA
  • Publication number: 20200089064
    Abstract: An active matrix substrate of a display device includes a substrate, a pixel TFT supported on a major surface side of the substrate, a gate line extending in a first direction, and a source line extending in a second direction that intersects to the first direction. The pixel TFT is a top gate configuration TFT that includes an oxide semiconductor layer which includes a channel region and a gate electrode which is electrically coupled with the gate line and which is provided on the oxide semiconductor layer with a gate insulating layer interposed therebetween. The active matrix substrate further includes a light shielding line which is provided between the substrate and the oxide semiconductor layer and which is provided with a predetermined potential.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 19, 2020
    Inventors: Junichi MORINAGA, Hikaru YOSHINO
  • Publication number: 20200089069
    Abstract: An active matrix substrate includes a first TFT of a peripheral circuit and a second TFT arranged in each pixel, wherein: the first TFT is a top gate or double gate TFT that includes an upper gate electrode on a portion of a first oxide semiconductor layer with a gate insulating layer interposed therebetween; the second TFT is a bottom gate TFT that includes a second lower gate electrode arranged on the substrate side of a second oxide semiconductor layer with a lower insulating layer interposed therebetween and includes no gate electrode on the second oxide semiconductor layer; the second TFT including: an island-shaped insulator layer that is arranged on a portion of the second oxide semiconductor layer so as to overlap with at least a portion of the second lower gate electrode, as seen from a direction normal to the substrate; an upper insulating layer that is arranged on the second oxide semiconductor layer and the island-shaped insulator layer; and a source electrode that is arranged on the upper insulat
    Type: Application
    Filed: September 16, 2019
    Publication date: March 19, 2020
    Inventors: Junichi MORINAGA, Hikaru YOSHINO
  • Publication number: 20200089037
    Abstract: A method for manufacturing an active matrix substrate including a thin film transistor disposed for each pixel, and a first electrode and a first wiring line for touchscreen panel function includes: (A) a step of forming an oxide semiconductor layer, a gate insulating layer, and a gate electrode on a substrate; (B) a step of forming an insulating layer covering the gate electrode, the gate insulating layer, and the oxide semiconductor layer, and having a source-side aperture and a drain-side aperture through which portions of the oxide semiconductor layer are exposed; (C) a step of forming a source electrode within the source-side aperture and a drain electrode within the drain-side aperture; (D) a step of forming an interlayer insulating layer including an organic insulating layer and having a first contact hole through which a portion of the drain electrode is exposed; (E) a step of forming a first transparent electrically conductive film on the interlayer insulating layer and within the first contact hole;
    Type: Application
    Filed: September 16, 2019
    Publication date: March 19, 2020
    Inventors: Hikaru YOSHINO, Junichi MORINAGA, Tetsuo KIKUCHI, Kengo HARA
  • Publication number: 20190258124
    Abstract: The present invention provides a liquid crystal display device which includes: a first substrate; a second substrate; and a light-shielding member disposed between adjacent sub-pixels having different colors, the first substrate includes a second electrode provided with a slit, the slit includes a main slit extending in a first direction and a sub-slit extending in a second direction, when the light-shielding member is provided on the first substrate, the light-shielding member is widened on a side of a closer sub-slit among the sub-slits formed in the sub-pixels that have different colors and disposed on both sides of the light-shielding member, and the light-shielding member is not widened on a side of a farther sub-slit, and when the light-shielding member is provided on the second substrate, the light-shielding member is widened on the side opposite to the case of the first substrate.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 22, 2019
    Inventors: Junichi MORINAGA, Hikaru YOSHINO, Shogo SUZUKI
  • Publication number: 20190146269
    Abstract: A color filter substrate includes a light transmissive substrate, a light blocking layer, a light transmissive layer, and a color layer. The light blocking layer is formed on the light transmissive substrate. The light transmissive layer is formed along an edge of the light blocking layer on the light transmissive substrate. The color layer passes rays of visible light and is tinted a predefined color so that the rays passing therethrough exhibit a predefined color. The color layer includes a section disposed on a top surface of the light transmissive substrate in a blank area and an edge section extending from the section in the blank area over the light transmissive layer and a section of the light blocking layer. A thickness of a section of the light transmissive layer on a blank area side is less than a thickness of the light blocking layer.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 16, 2019
    Inventors: KATSUHIRO MIKUMO, JUNICHI MORINAGA, HIKARU YOSHINO