Abstract: A semiconductor device includes a fuse wire, a portion to be fused that overlies the fuse wire with an insulation film interposed therebetween, and a plug connecting the portion to be fused and the fuse wire together. The portion to be fused underlies an insulation film having a thickness, and the fuse wire underlies an insulation film having a thickness larger than that of the insulation film overlying the portion to be fused. The insulation film overlying the fuse wire has a thickness sufficient to prevent a laser beam from blowing the fuse wire.

Abstract: A synchronous SRAM includes a register sequentially providing data signals of the burst length in a test mode, and a transfer circuit applying data signals output from the register to a memory array for burst-writing, and providing to an external source via an IO buffer a data signal read out in a burst manner later than the burst writing by 1 clock cycle. It is not necessary to additionally apply a data signal for writing. The required number of address signals can be reduced. Thus, testing can be simplified.

Abstract: A semiconductor device includes a fuse wire, a portion to be fused that overlies the fuse wire with an insulation film interposed therebetween, and a plug connecting the portion to be fused and the fuse wire together. The portion to be fused underlies an insulation film having a thickness, and the fuse wire underlies an insulation film having a thickness larger than that of the insulation film overlying the portion to be fused. The insulation film overlying the fuse wire has a thickness sufficient to prevent a laser beam from blowing the fuse wire.

Abstract: A semiconductor storage device is provided with a memory cell array and redundant cell arrays. Each of redundancy address program circuits that are provided for the respective redundant cell arrays produces a redundancy selection signal for selection of the corresponding redundant cell array. An address selection circuit selects an address of the memory cell array corresponding to an address selection signal if none of the redundancy address program circuits produce redundancy selection signals. Redundant cell array selecting circuits set priority ranks for the respective redundant cell arrays, and select only a redundant cell array having a highest priority rank at the time of receiving, from the redundancy address program circuits, redundancy selection signals for selection of two or more redundant cell arrays for the same address.

Abstract: A synchronous SRAM includes a register sequentially providing data signals of the burst length in a test mode, and a transfer circuit applying data signals output from the register to a memory array for burst-writing, and providing to an external source via an IO buffer a data signal read out in a burst manner later than the burst writing by 1 clock cycle. It is not necessary to additionally apply a data signal for writing. The required number of address signals can be reduced. Thus, testing can be simplified.