Abstract: A via model generation method includes: acquiring via arrangement information including a hole diameter of a via formed in a board including a plurality of wiring layers, a clearance distance between a ground conductor formed in one wiring layer of the plurality of wiring layers and the via, and a ground via distance between the via and a ground via coupled to the ground conductor; acquiring board information including a relative dielectric constant of the board; calculating a capacitance component of the via by a first electromagnetic field analysis using the hole diameter of the via, the clearance distance, and the relative dielectric constant of the board; calculating an inductance component of the via by a second electromagnetic field analysis using the hole diameter of the via, the ground via distance, and the relative dielectric constant of the board; and generating a via model including the capacitance and inductance components.

Abstract: An information processing device include: a memory; and one or more processors which are coupled to the memory, wherein the one or more processors performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate; and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes determining a relative permittivity of the substrate in a division position of a variation range of the relative permittivity of the substrate such that a variation range of a propagation delay time of the signal waveform corresponding to the variation range of the relative permittivity of the substrate is divided at even intervals; generating an analysis model corresponding to the relative permittivity of the substrate in the determined division position; and performing waveform analysis on the signal waveform using the generated analysis model.

Abstract: A via model generation method includes: acquiring via arrangement information including a hole diameter of a via formed in a board including wiring layers, clearance distance between a ground conductor formed in one of the wiring layers and the via, and ground via distance between the via and a ground via coupled to the ground conductor; acquiring, by a computer, board information including a relative dielectric constant of the board; calculating a capacitance component of the via by a first electromagnetic field analysis with use of the hole diameter of the via, the clearance distance, and the relative dielectric constant of the board; calculating an inductance component of the via by a second electromagnetic field analysis with use of the hole diameter of the via, the ground via distance, and the relative dielectric constant of the board; and generating a via model including the capacitance component and the inductance component.

Abstract: An information processing device includes a memory; and one or more processors which are coupled to the memory and configured to performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate, and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes generating analysis models of a plurality of respective combinations of variations in a plurality of kinds of elements which have an influence on the quality of the signal waveform; calculating impulse-response-waveforms of the plurality of respective combinations using the generated analysis models; calculating the noise amount of the plurality of respective combinations based on the calculated impulse-response-waveforms; selecting a combination, in which the calculated noise amount is the largest, as a worst case in the plurality of combinations; and performing signal waveform-transition-analysis on the selected worst case.

Abstract: An information processing device includes a memory; and one or more processors which are coupled to the memory and configured to performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate, and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes generating analysis models of a plurality of respective combinations of variations in a plurality of kinds of elements which have an influence on the quality of the signal waveform; calculating impulse-response-waveforms of the plurality of respective combinations using the generated analysis models; calculating the noise amount of the plurality of respective combinations based on the calculated impulse-response-waveforms; selecting a combination, in which the calculated noise amount is the largest, as a worst case in the plurality of combinations; and performing signal waveform-transition-analysis on the selected worst case.

Abstract: An information processing device include: a memory; and one or more processors which are coupled to the memory, wherein the one or more processors performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate; and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes determining a relative permittivity of the substrate in a division position of a variation range of the relative permittivity of the substrate such that a variation range of a propagation delay time of the signal waveform corresponding to the variation range of the relative permittivity of the substrate is divided at even intervals; generating an analysis model corresponding to the relative permittivity of the substrate in the determined division position; and performing waveform analysis on the signal waveform using the generated analysis model.

Abstract: An eye pattern is generated by: simulating a rising step response to a rising step signal input into the circuit and a falling step response to a falling step signal input into the circuit; analyzing a result of the simulating of the rising step response and the falling step response; generating, on the basis of a result of the analyzing, an upper-part test pattern that defines a shape of an upper part of an eye of an eye pattern and a lower-part test pattern that defines a shape of a lower part of the eye of the eye pattern; and simulating a response to the upper-part test pattern and the lower-part test pattern both input into the circuit. This procedure rapidly generates a precise eye pattern.

Abstract: An eye pattern is generated by: simulating a rising step response to a rising step signal input into the circuit and a falling step response to a falling step signal input into the circuit; analyzing a result of the simulating of the rising step response and the falling step response; generating, on the basis of a result of the analyzing, an upper-part test pattern that defines a shape of an upper part of an eye of an eye pattern and a lower-part test pattern that defines a shape of a lower part of the eye of the eye pattern; and simulating a response to the upper-part test pattern and the lower-part test pattern both input into the circuit. This procedure rapidly generates a precise eye pattern.

Abstract: A design-change-target-circuit detecting unit inputs circuit information including an element model describing an electronic circuit to detect an electronic circuit using a changed element model. A determining unit compares a characteristic of an element model before change and that of the element model after change. An analysis-necessity deciding unit decides whether waveform analysis is necessary, and when determining that waveform analysis is necessary, makes an instruction for waveform analysis of the electronic circuit using the element model after change.

Abstract: The apparatus comprises the syntax checking section that checks the syntax of a device model according to a check table showing the relation between the syntax of the device model showing electrical characteristics of a semiconductor device and an amendment when deviating from the syntax. The syntax error amendment creating section corrects the device model according to a corresponding amendment when a description deviating from the syntax is checked by the syntax checking section.

Abstract: In a simulation considering a skin effect, a signal conductor is vertically and horizontally divided by faces parallel to the surface of the signal conductor, which are set so that intervals are smaller as the faces are nearer to the surface, and larger as the faces are farther from the surface. Also a ground conductor is vertically divided with a similar method, and an integration calculation is made, so that the resistance of the signal conductor, which corresponds to a given frequency, is obtained.

Abstract: In a simulation considering a skin effect, a signal conductor is vertically and horizontally divided by faces parallel to the surface of the signal conductor, which are set so that intervals are smaller as the faces are nearer to the surface, and larger as the faces are farther from the surface. Also a ground conductor is vertically divided with a similar method, and an integration calculation is made, so that the resistance of the signal conductor, which corresponds to a given frequency, is obtained.

Abstract: The apparatus comprises the syntax checking section that checks the syntax of a device model according to a check table showing the relation between the syntax of the device model showing electrical characteristics of a semiconductor device and an amendment when deviating from the syntax. The syntax error amendment creating section corrects the device model according to a corresponding amendment when a description deviating from the syntax is checked by the syntax checking section.