Abstract: A vector processor includes a coefficient memory and a processor. The processor has an Instruction Set Architecture (ISA), which includes an instruction that approximates a mathematical function by a polynomial. The processor is configured to approximate the mathematical function over an argument, by reading one or more coefficients of the polynomial from the coefficient memory and evaluating the polynomial at the argument using the coefficients.

Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Abstract: Methods, systems, and computer program products for managing memory of a passive optical network (PON) are provided herein. The method includes the steps of receiving a plurality of data packets from a stream of packets. A plurality of packet descriptors associated with each data packet is stored in a configurable first queue. The first queue includes a plurality of cache slots and is managed in an internal memory. A state of the first queue is identified. In response to the state of the first queue meeting a predetermined threshold, packet descriptors from a tail cache slot of the first queue are transferred to a second queue. The second queue is managed in an external memory.

Abstract: Embodiments are directed towards modifying a quality of an image without affecting a bit rate associated with a video sequence of images. For each macro-block (MB) or sub-block within a MB for a target image to be encoded, various statistics are determined for a luminance component and chrominance components that provide at least average values for the chrominance components that may then be used to identify saturation thresholds. The saturation thresholds are used to determine a Qlevel. An average Qlevel from at least a previous frame is used to generate a Q modulation factor that may be combined with an activity based modulation factor and/or variance based modulation factor, or used singly. The final quantizer is calculated by bit-rate controller base quantizer multiplied by the Q modulation factor, and may be used to encode a MB or sub-block within a MB.

Abstract: Methods, systems, and computer program products for managing memory of a passive optical network (PON) are provided herein. The method includes the steps of receiving a plurality of data packets from a stream of packets. A plurality of packet descriptors associated with each data packet is stored in a configurable first queue. The first queue includes a plurality of cache slots and is managed in an internal memory. A state of the first queue is identified. In response to the state of the first queue meeting a predetermined threshold, packet descriptors from a tail cache slot of the first queue are transferred to a second queue. The second queue is managed in an external memory.