Patents by Inventor Hillel Avni
Hillel Avni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11614959Abstract: The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.Type: GrantFiled: January 17, 2018Date of Patent: March 28, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Hillel Avni, Eliezer Levy, Avi Mendelson, Zuguang Wu
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Patent number: 11474995Abstract: A system for managing abort events of Hardware Transactional Memory (HTM) transactions to an in-memory database, comprising a processor adapted to control a plurality of abort events of a plurality of database transactions held concurrently to a shared in-memory database and a method for managing abort events comprising analyzing a metadata record associated with each potential abort event, where the metadata record comprises a row ID value and a row version value of a certain one of a plurality of rows of a database that is concurrently accessed by an aborting HTM transaction and another HTM transaction, comparing the row ID value and the row version value to a local ID value and a local version value of the aborting HTM transaction and determining a contention condition between the aborting HTM transaction and the other HTM transaction.Type: GrantFiled: October 18, 2019Date of Patent: October 18, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Hillel Avni, Aharon Avitzur
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Patent number: 11354307Abstract: There is provided a database management system, comprising: a multicore processor, a shared memory, a partitioned memory, and a database engine adapted to execute at least one transaction worker thread managing transaction states and database indexes in the shared memory using a cache coherency mechanism, and execute at least one partition manager thread for handling database access actions submitted by the at least one transaction worker thread to access a database in the partitioned memory, the cache coherency mechanism being disabled in the partitioned memory; wherein the at least one transaction worker thread and the at least one partition manager thread are executed simultaneously on the multicore processor.Type: GrantFiled: March 21, 2018Date of Patent: June 7, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Israel Gold, Hillel Avni, Antonios Iliopoulos
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Patent number: 10990628Abstract: In one embodiment, a system for managing a skiplist includes processors arranged for parallel execution of threads, a shared memory storing a skiplist arranged as an ordered set of nodes, and at least one transaction execution thread executed by at least one of the plurality of processors. The at least one transaction execution thread is to execute a range-query operation to identify at least one node of the ordered set of nodes between a first lower key value and a second upper key value, the key-range operation executed by an execution phase and a commit phase, wherein during the execution phase the at least one transaction execution thread traverses nodes of the skiplist in a lock-free state, wherein during the commit phase the at least one transaction execution thread executes a commit protocol that guarantees transaction consistency of the skiplist structure and validates consistency of the range-query operation.Type: GrantFiled: March 6, 2019Date of Patent: April 27, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Israel Gold, Hillel Avni
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Publication number: 20200081883Abstract: A system for managing abort events of Hardware Transactional Memory (HTM) transactions to an in-memory database, comprising a processor adapted to control a plurality of abort events of a plurality of database transactions held concurrently to a shared in-memory database and a method for managing abort events comprising analyzing a metadata record associated with each potential abort event, where the metadata record comprises a row ID value and a row version value of a certain one of a plurality of rows of a database that is concurrently accessed by an aborting HTM transaction and another HTM transaction, comparing the row ID value and the row version value to a local ID value and a local version value of the aborting HTM transaction and determining a contention condition between the aborting HTM transaction and the other HTM transaction.Type: ApplicationFiled: October 18, 2019Publication date: March 12, 2020Inventors: Hillel Avni, Aharon Avitzur
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Publication number: 20200050601Abstract: A system for utilizing a Hardware Transactional Memory (HTM) for an in-memory database, comprising a processor adapted to execute a plurality of database transactions held concurrently to a shared in-memory database by splitting each of the plurality of database transactions into a plurality of HTM transactions, wherein each of the plurality of HTM transactions is executed atomically to access one of a plurality of rows of a database, and for each of the plurality of HTM transactions perform the following operations—access a certain one of the plurality of rows, for a read HTM transaction, fetch content of a previous version of the certain row in case of a detection of another write HTM transaction concurrently writing the certain row, and for a write HTM transaction abort the write HTM transaction at initiation in case of the detection, and validate and commit the each HTM transaction through an additional HTM transaction.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Hillel AVNI, Aharon AVITZUR
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Publication number: 20190205344Abstract: In one embodiment, a system for managing a skiplist includes processors arranged for parallel execution of threads, a shared memory storing a skiplist arranged as an ordered set of nodes, and at least one transaction execution thread executed by at least one of the plurality of processors. The at least one transaction execution thread is to execute a range-query operation to identify at least one node of the ordered set of nodes between a first lower key value and a second upper key value, the key-range operation executed by an execution phase and a commit phase, wherein during the execution phase the at least one transaction execution thread traverses nodes of the skiplist in a lock-free state, wherein during the commit phase the at least one transaction execution thread executes a commit protocol that guarantees transaction consistency of the skiplist structure and validates consistency of the range-query operation.Type: ApplicationFiled: March 6, 2019Publication date: July 4, 2019Inventors: Israel GOLD, Hillel AVNI
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Publication number: 20180268027Abstract: There is provided a database management system, comprising: a multicore processor, a shared memory, a partitioned memory, and a database engine adapted to execute at least one transaction worker thread managing transaction states and database indexes in the shared memory using a cache coherency mechanism, and execute at least one partition manager thread for handling database access actions submitted by the at least one transaction worker thread to access a database in the partitioned memory, the cache coherency mechanism being disabled in the partitioned memory; wherein the at least one transaction worker thread and the at least one partition manager thread are executed simultaneously on the multicore processor.Type: ApplicationFiled: March 21, 2018Publication date: September 20, 2018Inventors: Israel GOLD, Hillel AVNI, Antonios ILIOPOULOS
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Publication number: 20180143850Abstract: The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.Type: ApplicationFiled: January 17, 2018Publication date: May 24, 2018Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Hillel AVNI, Eliezer LEVY, Avi MENDELSON, Zuguang WU
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Patent number: 9058206Abstract: A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.Type: GrantFiled: June 19, 2008Date of Patent: June 16, 2015Assignee: Freescale emiconductor, Inc.Inventors: Hillel Avni, Serge Lamikhov, Dov Levenglick
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Patent number: 8966490Abstract: A system, computer program and a method for scheduling a processing entity task in a multiple-processing entity system, the method includes initializing a scheduler; receiving a task data structure indicative that a pre-requisite to an execution of task to be executed by a processing entity is a completion of a peripheral task that is executed by a peripheral; wherein the peripheral updates a peripheral task completion indicator once the peripheral task is completed; wherein the peripheral task completion indicator is accessible by the scheduler; and scheduling, by the scheduler, the task in response to the peripheral task completion indicator.Type: GrantFiled: June 19, 2008Date of Patent: February 24, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
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Patent number: 8850446Abstract: A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility of each task data structure out of a group of data structures to be moved from a sorted tasks queue to a ready for execution task; updating a value, during each scheduling iteration, of a queue starvation watermark value of each task data structure that is not eligible to move to a running tasks queue, until a queue starvation watermark value of a certain task data structure out of the group reaches a queue starvation watermark threshold; and generating a task starvation indication if during an additional number of scheduling iterations, the certain task data structure is still prevented from being moved to a running tasks queue, and the additional number is responsive to a task starvation watermark.Type: GrantFiled: June 19, 2008Date of Patent: September 30, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
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Publication number: 20110154344Abstract: A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.Type: ApplicationFiled: June 19, 2008Publication date: June 23, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Hillel Avni, Serge Lamikhov, Dov Levenglick
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Publication number: 20110099552Abstract: A system, computer program and a method, the method for scheduling processor entity tasks in a multiple-processing entity system includes: receiving task data structures from multiple processing entities; wherein a task data structure represents a task to be executed by a processing entity; and scheduling an execution of the tasks by a multiple purpose entity.Type: ApplicationFiled: June 19, 2008Publication date: April 28, 2011Applicant: Freescale Semiconductor, IncInventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
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Publication number: 20110072434Abstract: A system, computer program and a method for scheduling a processing entity task in a multiple-processing entity system, the method includes initializing a scheduler; receiving a task data structure indicative that a pre-requisite to an execution of task to be executed by a processing entity is a completion of a peripheral task that is executed by a peripheral; wherein the peripheral updates a peripheral task completion indicator once the peripheral task is completed; wherein the peripheral task completion indicator is accessible by the scheduler; and scheduling, by the scheduler, the task in response to the peripheral task completion indicator.Type: ApplicationFiled: June 19, 2008Publication date: March 24, 2011Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
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Publication number: 20090320032Abstract: A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility of each task data structure out of a group of data structures to be moved from a sorted tasks queue to a ready for execution task; updating a value, during each scheduling iteration, of a queue starvation watermark value of each task data structure that is not eligible to move to a running tasks queue, until a queue starvation watermark value of a certain task data structure out of the group reaches a queue starvation watermark threshold; and generating a task starvation indication if during an additional number of scheduling iterations, the certain task data structure is still prevented from being moved to a running tasks queue, wherein the additional number is responsive to a task starvation watermark.Type: ApplicationFiled: June 19, 2008Publication date: December 24, 2009Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz