Patents by Inventor Hillel Avni

Hillel Avni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11614959
    Abstract: The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 28, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hillel Avni, Eliezer Levy, Avi Mendelson, Zuguang Wu
  • Patent number: 11474995
    Abstract: A system for managing abort events of Hardware Transactional Memory (HTM) transactions to an in-memory database, comprising a processor adapted to control a plurality of abort events of a plurality of database transactions held concurrently to a shared in-memory database and a method for managing abort events comprising analyzing a metadata record associated with each potential abort event, where the metadata record comprises a row ID value and a row version value of a certain one of a plurality of rows of a database that is concurrently accessed by an aborting HTM transaction and another HTM transaction, comparing the row ID value and the row version value to a local ID value and a local version value of the aborting HTM transaction and determining a contention condition between the aborting HTM transaction and the other HTM transaction.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 18, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hillel Avni, Aharon Avitzur
  • Patent number: 11354307
    Abstract: There is provided a database management system, comprising: a multicore processor, a shared memory, a partitioned memory, and a database engine adapted to execute at least one transaction worker thread managing transaction states and database indexes in the shared memory using a cache coherency mechanism, and execute at least one partition manager thread for handling database access actions submitted by the at least one transaction worker thread to access a database in the partitioned memory, the cache coherency mechanism being disabled in the partitioned memory; wherein the at least one transaction worker thread and the at least one partition manager thread are executed simultaneously on the multicore processor.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: June 7, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Israel Gold, Hillel Avni, Antonios Iliopoulos
  • Patent number: 10990628
    Abstract: In one embodiment, a system for managing a skiplist includes processors arranged for parallel execution of threads, a shared memory storing a skiplist arranged as an ordered set of nodes, and at least one transaction execution thread executed by at least one of the plurality of processors. The at least one transaction execution thread is to execute a range-query operation to identify at least one node of the ordered set of nodes between a first lower key value and a second upper key value, the key-range operation executed by an execution phase and a commit phase, wherein during the execution phase the at least one transaction execution thread traverses nodes of the skiplist in a lock-free state, wherein during the commit phase the at least one transaction execution thread executes a commit protocol that guarantees transaction consistency of the skiplist structure and validates consistency of the range-query operation.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 27, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Israel Gold, Hillel Avni
  • Publication number: 20200081883
    Abstract: A system for managing abort events of Hardware Transactional Memory (HTM) transactions to an in-memory database, comprising a processor adapted to control a plurality of abort events of a plurality of database transactions held concurrently to a shared in-memory database and a method for managing abort events comprising analyzing a metadata record associated with each potential abort event, where the metadata record comprises a row ID value and a row version value of a certain one of a plurality of rows of a database that is concurrently accessed by an aborting HTM transaction and another HTM transaction, comparing the row ID value and the row version value to a local ID value and a local version value of the aborting HTM transaction and determining a contention condition between the aborting HTM transaction and the other HTM transaction.
    Type: Application
    Filed: October 18, 2019
    Publication date: March 12, 2020
    Inventors: Hillel Avni, Aharon Avitzur
  • Publication number: 20200050601
    Abstract: A system for utilizing a Hardware Transactional Memory (HTM) for an in-memory database, comprising a processor adapted to execute a plurality of database transactions held concurrently to a shared in-memory database by splitting each of the plurality of database transactions into a plurality of HTM transactions, wherein each of the plurality of HTM transactions is executed atomically to access one of a plurality of rows of a database, and for each of the plurality of HTM transactions perform the following operations—access a certain one of the plurality of rows, for a read HTM transaction, fetch content of a previous version of the certain row in case of a detection of another write HTM transaction concurrently writing the certain row, and for a write HTM transaction abort the write HTM transaction at initiation in case of the detection, and validate and commit the each HTM transaction through an additional HTM transaction.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: Hillel AVNI, Aharon AVITZUR
  • Publication number: 20190205344
    Abstract: In one embodiment, a system for managing a skiplist includes processors arranged for parallel execution of threads, a shared memory storing a skiplist arranged as an ordered set of nodes, and at least one transaction execution thread executed by at least one of the plurality of processors. The at least one transaction execution thread is to execute a range-query operation to identify at least one node of the ordered set of nodes between a first lower key value and a second upper key value, the key-range operation executed by an execution phase and a commit phase, wherein during the execution phase the at least one transaction execution thread traverses nodes of the skiplist in a lock-free state, wherein during the commit phase the at least one transaction execution thread executes a commit protocol that guarantees transaction consistency of the skiplist structure and validates consistency of the range-query operation.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Inventors: Israel GOLD, Hillel AVNI
  • Publication number: 20180268027
    Abstract: There is provided a database management system, comprising: a multicore processor, a shared memory, a partitioned memory, and a database engine adapted to execute at least one transaction worker thread managing transaction states and database indexes in the shared memory using a cache coherency mechanism, and execute at least one partition manager thread for handling database access actions submitted by the at least one transaction worker thread to access a database in the partitioned memory, the cache coherency mechanism being disabled in the partitioned memory; wherein the at least one transaction worker thread and the at least one partition manager thread are executed simultaneously on the multicore processor.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 20, 2018
    Inventors: Israel GOLD, Hillel AVNI, Antonios ILIOPOULOS
  • Publication number: 20180143850
    Abstract: The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.
    Type: Application
    Filed: January 17, 2018
    Publication date: May 24, 2018
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hillel AVNI, Eliezer LEVY, Avi MENDELSON, Zuguang WU
  • Patent number: 9058206
    Abstract: A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: June 16, 2015
    Assignee: Freescale emiconductor, Inc.
    Inventors: Hillel Avni, Serge Lamikhov, Dov Levenglick
  • Patent number: 8966490
    Abstract: A system, computer program and a method for scheduling a processing entity task in a multiple-processing entity system, the method includes initializing a scheduler; receiving a task data structure indicative that a pre-requisite to an execution of task to be executed by a processing entity is a completion of a peripheral task that is executed by a peripheral; wherein the peripheral updates a peripheral task completion indicator once the peripheral task is completed; wherein the peripheral task completion indicator is accessible by the scheduler; and scheduling, by the scheduler, the task in response to the peripheral task completion indicator.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
  • Patent number: 8850446
    Abstract: A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility of each task data structure out of a group of data structures to be moved from a sorted tasks queue to a ready for execution task; updating a value, during each scheduling iteration, of a queue starvation watermark value of each task data structure that is not eligible to move to a running tasks queue, until a queue starvation watermark value of a certain task data structure out of the group reaches a queue starvation watermark threshold; and generating a task starvation indication if during an additional number of scheduling iterations, the certain task data structure is still prevented from being moved to a running tasks queue, and the additional number is responsive to a task starvation watermark.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
  • Publication number: 20110154344
    Abstract: A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.
    Type: Application
    Filed: June 19, 2008
    Publication date: June 23, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Hillel Avni, Serge Lamikhov, Dov Levenglick
  • Publication number: 20110099552
    Abstract: A system, computer program and a method, the method for scheduling processor entity tasks in a multiple-processing entity system includes: receiving task data structures from multiple processing entities; wherein a task data structure represents a task to be executed by a processing entity; and scheduling an execution of the tasks by a multiple purpose entity.
    Type: Application
    Filed: June 19, 2008
    Publication date: April 28, 2011
    Applicant: Freescale Semiconductor, Inc
    Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
  • Publication number: 20110072434
    Abstract: A system, computer program and a method for scheduling a processing entity task in a multiple-processing entity system, the method includes initializing a scheduler; receiving a task data structure indicative that a pre-requisite to an execution of task to be executed by a processing entity is a completion of a peripheral task that is executed by a peripheral; wherein the peripheral updates a peripheral task completion indicator once the peripheral task is completed; wherein the peripheral task completion indicator is accessible by the scheduler; and scheduling, by the scheduler, the task in response to the peripheral task completion indicator.
    Type: Application
    Filed: June 19, 2008
    Publication date: March 24, 2011
    Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
  • Publication number: 20090320032
    Abstract: A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility of each task data structure out of a group of data structures to be moved from a sorted tasks queue to a ready for execution task; updating a value, during each scheduling iteration, of a queue starvation watermark value of each task data structure that is not eligible to move to a running tasks queue, until a queue starvation watermark value of a certain task data structure out of the group reaches a queue starvation watermark threshold; and generating a task starvation indication if during an additional number of scheduling iterations, the certain task data structure is still prevented from being moved to a running tasks queue, wherein the additional number is responsive to a task starvation watermark.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz