Patents by Inventor Himanshu Choudhary

Himanshu Choudhary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High throughput circuit architecture for hardware acceleration
    Patent number: 11386034
    Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Xilinx, Inc.
    Inventors: Sonal Santan, Ravi N. Kurlagunda, Min Ma, Himanshu Choudhary, Manjunath Chepuri, Cheng Zhen, Pranjal Joshi, Sebastian Turullols, Amit Kumar, Kaustuv Manji, Ravinder Sharma, Ch Vamshi Krishna
  • HIGH THROUGHPUT CIRCUIT ARCHITECTURE FOR HARDWARE ACCELERATION
    Publication number: 20220138140
    Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Xilinx, Inc.
    Inventors: Sonal Santan, Ravi N. Kurlagunda, Min Ma, Himanshu Choudhary, Manjunath Chepuri, Cheng Zhen, Pranjal Joshi, Sebastian Turullols, Amit Kumar, Kaustuv Manji, Ravinder Sharma, Ch Vamshi Krishna