Abstract: An on-chip stuck-at fault detector in an integrated circuit using a test circuit for critical path testing can include a sequence circuit having a first sequential circuit and a second sequential circuit to sensitize the critical path between a source sequential circuit and a destination sequential circuit, an analyzer circuit for capturing an output from the destination sequential circuit and comparing a signal between the destination sequential circuit and the analyzer circuit at predetermined clock cycles, and a controller for strobing the analyzer circuit at the predetermined clock cycles. The first sequence and second circuits can both be initialized to a zero mode (e.g., x=0 and y=0). Thus, no stuck-at faults are determined if the destination sequential circuit and an analyzer sequential circuit in the analyzer circuit have different values and a zero result is captured at a sticky-bit flip flop.

Abstract: A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.

Abstract: A test circuit in an integrated circuit (200 or 300) is used for verifying a critical path of a circuit (230) under test. The test circuit can include a sequence generator (202) generating a data signal for the critical path, a source sequential circuit (208) for receiving the data signal coupled to an input of the critical path, a destination sequential circuit (210 or 310) for receiving an output of the critical path, and an analyzer circuit (212 or 312) for verification of timing of the critical path by measuring timing from the source sequential circuit to a clock enable pin (209) or a set/reset pin (309) of the destination sequential circuit. The test circuit can further include a controller circuit (220) for strobing a comparison circuit (218) in the analyzer circuit at a predetermined clock time. The integrated circuit can be part of an FPGA or FPGA fabric.

Abstract: A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.

Abstract: Signal phase adjustment for duty cycle control is described. A first sample clock signal and a second sample clock signal are provided. A first phase signal and a second phase signal are generated responsive to the first sample clock signal, where the first phase signal is out of phase with respect to the second phase signal. The second sample clock signal configured to be swept in phase in relation to the first phase signal. A combined signal is generated where the combined signal has a duty cycle associated with the first phase signal and the second phase signal in combination. A first counter and a second counter are clocked responsive to the second sample clock signal to count. A first count from the first counter is divided by a second count from the second counter to obtain the duty cycle associated with the combined signal.

Abstract: A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated circuit. The first path is coupled in a ring oscillator, and a first delay is determined. A second path is formed by coupling a second portion of the conductive lines together. The second portion is the first portion except for at least a first conductive line in the first portion of the conductive lines being swapped for a second conductive line. The second conductive line is associated with a second region of the integrated circuit. The second path is coupled in the ring oscillator circuit. A second delay is determined, and an incremental difference between the first delay and the second delay may be determined.

Abstract: Cross-correlation of delay line characteristics is described. An integrated circuit for cross-correlation testing includes: a first ring oscillator and a second ring oscillator. The first ring oscillator includes a first test circuit, and the second ring oscillator includes a second test circuit. The first test circuit is coupled via first programmable interconnects to first ring oscillator circuitry, and the second test circuit is coupled via second programmable interconnects to second ring oscillator circuitry. The first test circuit includes a first programmable delay line, and the second test circuit includes a second programmable delay line. The first test circuit and the second test circuit are configured to provide separately controllable outputs for cross-correlation as between the first programmable delay line and the second programmable delay line.

Abstract: A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to sample the logic value of a test signal after the test signal has traversed a path under test (PUT). A counter is used to determine the number of logic high valued samples and the number of logic low valued samples during a test period. A ratio is then taken to determine the resulting duty cycle for the test period.

Abstract: First and second clock signals are provided to first and second sequential circuits, where the first and second clock signals are inversely coupled to logic high and low levels for clocking of the first and second sequential circuits. A third sequential circuit is clocked responsive to a first output from the first sequential circuit and receives first signature data. A fourth sequential circuit is clocked responsive to a second output from the second sequential circuit and receives second signature data. A third output from the third sequential circuit is monitored responsive to the first signature data and the first output. A fourth output from the fourth sequential circuit is monitored responsive to the second signature data and the second output. Whether the first clock signal and the second clock signal are phase aligned may be determined responsive to the third output and the fourth output.

Abstract: Testing signal propagation delay of a shift register circuit is described. A ring oscillator has a first sequential element, a second sequential element, and a shift register circuit. The shift register circuit is coupled in series between the first sequential element and the second sequential element. The shift register circuit includes the at least one shift register and combinational logic coupled to the at least one shift register. The at least one shift register is configured to store a test data pattern of alternating logic ones and zeros. The combinational logic is coupled to receive a data signal from the first sequential element of the ring oscillator and coupled to receive a shift output signal from the at least one shift register. The combinational logic is configured to provide an exclusive logic function.

Abstract: A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to obtain estimates of, for example, capacitive coupling of signal energy between various signal and clock routes within a programmable logic device (PLD). Progressively delayed/advanced samples are taken of a test signal transmitted through a victim net to form baseline test data. Samples of the test signal are then repeated in the presence of test signals transmitted through aggressor net(s) and compared to the baseline results to measure crosstalk distortion caused by capacitively coupled energy from the aggressor nets onto the victim net.

Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Abstract: A test oscillator circuit separately measures the signal propagation delay for both rising and falling edges through one or more multi-input combinatorial logic circuits. A number of components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component passes signal edges to a subsequent component in the ring, so the oscillator produces an oscillating test signal in which the period relates to the delays through the components. In some embodiments, the multi-input combinatorial logic circuits emulate tri-state buffers. These embodiments characterize the speed at which these logic circuits enable and disable signal paths.

Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.