Abstract: A method for verifying an electronic circuit design includes detecting a first issue in a register transfer level description of the electronic circuit design and receiving a selection to waive the first issue. The method also includes capturing the selection to waive the first issue in a memory, detecting, by a processing device, a second issue while generating a netlist or gate level description of the electronic circuit design, and based on determining that the selection to waive the first issue indicated in the memory applies to the second issue, suppressing or ignoring the second issue.

Abstract: A system receives a specification of a circuit design for performing simulation of the circuit design. The specification includes one or more prototyping statements. A prototyping statement is processed by simulation of the circuit design. The system generates a netlist graph based on the specification of the circuit design. The system ignores the prototyping statements while generating the netlist graph. The system modifies the netlist graph to incorporate the prototyping statements of the specification. The netlist graph is modified by adding at least a net to the netlist graph based on a prototyping statement. The system performs static analysis based on the modified netlist graph.