Abstract: A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: An example apparatus includes programmable circuitry configured to: determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage; determine a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage; determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

Abstract: A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: An example apparatus includes programmable circuitry configured to: determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage; determine a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage; determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

Abstract: An example analog-to-digital converter (ADC) includes first ADC circuitry, second ADC circuitry, and dither circuitry. The dither circuitry of the example ADC is to generate a first dither signal to produce a first dithered input signal at a first output coupled to an input of the first ADC circuitry, generate a second dither signal to produce a second dithered input signal at a second output coupled to an input of the second ADC circuitry, the first dither signal and the second dither signal to have opposite signs, and produce an output signal at a third output based on the first output of the first ADC circuitry and the second output of the second ADC circuitry.

Abstract: A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.

Abstract: An example analog-to-digital converter (ADC) includes first ADC circuitry, second ADC circuitry, and dither circuitry. The dither circuitry of the example ADC is to generate a first dither signal to produce a first dithered input signal at a first output coupled to an input of the first ADC circuitry, generate a second dither signal to produce a second dithered input signal at a second output coupled to an input of the second ADC circuitry, the first dither signal and the second dither signal to have opposite signs, and produce an output signal at a third output based on the first output of the first ADC circuitry and the second output of the second ADC circuitry.

Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.

Abstract: An example apparatus includes programmable circuitry configured to: determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage; determine a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage; determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.

Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.

Abstract: A cloud based network includes a plurality of nodes, each of which include at least one containerized microservice that enables intent-driven operation of the cloud based network. One or more resource controllers, each designated to manage a custom resource, communicate with a master controller of the node to manage operational and configuration states of the node and any microservices containerized within the node. The master enables a user to monitor and automate the management of microservices and the cloud based network as a whole. The containerized microservice architecture allows user customizable rendering of microservices, reconciliation of old and new versions of microservices, and facilitated management of a plurality of nodes.

Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.

Abstract: A cloud based network includes a plurality of nodes, each of which include at least one containerized microservice that enables intent-driven operation of the cloud based network. One or more resource controllers, each designated to manage a custom resource, communicate with a master controller of the node to manage operational and configuration states of the node and any microservices containerized within the node. The master enables a user to monitor and automate the management of microservices and the cloud based network as a whole. The containerized microservice architecture allows user customizable rendering of microservices, reconciliation of old and new versions of microservices, and facilitated management of a plurality of nodes.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.