Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

Abstract: Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.

Abstract: Disclosed is a DC voltage conversion circuit of a liquid crystal display apparatus, including: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltages applied to gates of the plurality of thin film transistors by inversion of a clock signal, in which each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto.

Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed are an oxide thin film transistor resistant to light and bias stress, and a method of manufacturing the same. The method includes forming a gate electrode on a substrate; forming a gate insulating layer on an upper part including the gate electrode; forming a source electrode and a drain electrode on the insulating layer; forming an active layer insulated from the gate electrode by the gate insulating layer and formed of an oxide semiconductor and a diffusion barrier film; and forming a protective layer on a portion of the source electrode and drain electrode and the upper part including the active layer, wherein the diffusion barrier film reduces movement of holes and prevents ionized oxygen vacancies from being diffused.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.