Abstract: A device includes: a plurality of first transistors included in a first current path, in a normal mode, between a first power node to which a positive supply voltage is configured to be applied and a second power node to which a negative supply voltage is configured to be applied; and a first protection transistor connected to a first node which two of the plurality of first transistors are connected to, wherein the first protection transistor is configured to be turned off in the normal mode and to be turned on to provide a protection voltage to the first node in a power down mode.

Abstract: A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

Abstract: A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

Abstract: A semiconductor device may include a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor, and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage. The failure detector may include a second bipolar junction transistor a current source configured to generate a bias current, a first resistor coupled between the current source and a emitter of the second bipolar junction transistor to generate the upper limit reference voltage, a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage, and a first and second comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and the lower limit reference voltage, respectively, to generate respective failure signals.

Abstract: A graph upscaling method and apparatus is disclosed. The graph upscaling apparatus may store, in a main memory, original graph data including topological data including a vertex and an edge, determine a parent edge using a hash function and the original graph data, and generate a new edge based on the determined parent edge. The graph upscaling apparatus may store, in a main memory, original graph data including topological data including a vertex and an edge, allocate identities (IDs) of edges to be generated to cores included in a central processing unit (CPU) based on the number of the cores, and generate new edges based on the IDs of the edges using a hash function and the original graph data.

Abstract: A beam deflector, a holographic display device including the beam deflector, and a method of driving the beam deflector are provided. The beam deflector includes first electrodes spaced apart from each other on a first substrate, second electrodes spaced apart from each other on a second substrate, a liquid crystal layer between the first substrate and the second substrate, and a controller configured to cause active prisms to be formed in the liquid crystal layer and to form a floating zone by turning off a voltage of at least one of the first electrode and the second electrode disposed between adjacent ones of the active prisms.

Abstract: Disclosed is a graph generating method and apparatus, the graph generating apparatus that may recognize one source vertex among a plurality of vertices, obtain the target number of at least one edge to generate from the source vertex, among the total target number of edges to generate between the vertices, obtain a recursive vector to be used repeatedly to generate the at least one edge, in a scope in which an existence of an edge for the source vertex needs to be verified, and generate the at least one edge between the source vertex and at least one destination vertex based on the target number and the recursive vector.

Abstract: A graph upscaling method and apparatus is disclosed. The graph upscaling apparatus may store, in a main memory, original graph data including topological data including a vertex and an edge, determine a parent edge using a hash function and the original graph data, and generate a new edge based on the determined parent edge. The graph upscaling apparatus may store, in a main memory, original graph data including topological data including a vertex and an edge, allocate identities (IDs) of edges to be generated to cores included in a central processing unit (CPU) based on the number of the cores, and generate new edges based on the IDs of the edges using a hash function and the original graph data.

Abstract: A beam deflector, a holographic display device including the beam deflector, and a method of driving the beam deflector are provided. The beam deflector includes first electrodes spaced apart from each other on a first substrate, second electrodes spaced apart from each other on a second substrate, a liquid crystal layer between the first substrate and the second substrate, and a controller configured to cause active prisms to be formed in the liquid crystal layer and to form a floating zone by turning off a voltage of at least one of the first electrode and the second electrode disposed between adjacent ones of the active prisms.

Abstract: Disclosed is a graph generating method and apparatus, the graph generating apparatus that may recognize one source vertex among a plurality of vertices, obtain the target number of at least one edge to generate from the source vertex, among the total target number of edges to generate between the vertices, obtain a recursive vector to be used repeatedly to generate the at least one edge, in a scope in which an existence of an edge for the source vertex needs to be verified, and generate the at least one edge between the source vertex and at least one destination vertex based on the target number and the recursive vector