Abstract: An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.

Abstract: An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.

Abstract: A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.

Abstract: A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.

Abstract: A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.

Abstract: A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.