Patents by Inventor Hin Fai Chau

Hin Fai Chau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9190384
    Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: November 17, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Shixi Louis Liu, Wenlong Ma, Frank Hin-Fai Chau, Barry Jia-Fu Lin
  • Publication number: 20140206149
    Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicant: TriQuint Semiconductor, Inc.
    Inventors: Shixi Louis Liu, Wenlong Ma, Frank Hin-Fai Chau, Barry Jia-Fu Lin
  • Patent number: 8718720
    Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: May 6, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Shixi Louis Liu, Wenlong Ma, Frank Hin-Fai Chau, Barry Jia-Fu Lin
  • Patent number: 7960097
    Abstract: A method of minimizing etch undercut and providing clean metal liftoff in subsequent metal deposition is provided. In one embodiment a bilayer resist mask is employed and used for etching of underlying substrate material and subsequent metal liftoff. In one embodiment, the top layer resist such as positive photoresist which is sensitive to selected range of energy, such as near UV or violet light, is first patterned by standard photolithography techniques and resist development in a first developer to expose portion of a bottom resist layer which is sensitive to a different selected range of energy, such as deep UV light. The exposed portion of the bottom layer resist is then removed by anisotropic etching such as oxygen reactive ion etching using the top layer resist as the etch mask to expose portion of the underlying substrate. This minimizes the undercut in the bottom resist around the top photoresist opening.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: June 14, 2011
    Assignee: Triquint Semiconductor, Inc.
    Inventors: Frank Hin Fai Chau, Yan Chen
  • Publication number: 20090111061
    Abstract: A method of minimizing etch undercut and providing clean metal liftoff in subsequent metal deposition is provided. In one embodiment a bilayer resist mask is employed and used for etching of underlying substrate material and subsequent metal liftoff. In one embodiment, the top layer resist such as positive photoresist which is sensitive to selected range of energy, such as near UV or violet light, is first patterned by standard photolithography techniques and resist development in a first developer to expose portion of a bottom resist layer which is sensitive to a different selected range of energy, such as deep UV light. The exposed portion of the bottom layer resist is then removed by anisotropic etching such as oxygen reactive ion etching using the top layer resist as the etch mask to expose portion of the underlying substrate. This minimizes the undercut in the bottom resist around the top photoresist opening.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventors: Frank Hin Fai Chau, Yan Chen
  • Patent number: 7012288
    Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: March 14, 2006
    Assignee: WJ Communications, Inc.
    Inventors: Chien Ping Lee, Hin Fai Chau, Nanlei Larry Wang, Clarence John Dunnrowicz, Yan Chen, Barry Jia-Fu Lin
  • Patent number: 6806513
    Abstract: The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: October 19, 2004
    Assignee: EIC Corporation
    Inventors: Hin Fai Chau, Clarence John Dunnrowicz, Yan Chen, Chien Ping Lee
  • Publication number: 20040188712
    Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (continuous or stepped) doping between the base region and the underlying subcollector region with the collector doping being lowest near the base and highest near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicant: EiC Corporation
    Inventors: Chien Ping Lee, Frank Hin Fai Chau, Nanlei Larry Wang, Clarence John Dunnrowicz, Yan Chen, Barry Jia-Fu Lin
  • Publication number: 20040065897
    Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: EiC Corporation
    Inventors: Chien Ping Lee, Hin Fai Chau, Nanlei Larry Wang, Clarence John Dunnrowicz, Yan Chen, Barry Jia-Fu Lin
  • Publication number: 20040065898
    Abstract: The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: EiC Corporation
    Inventors: Hin Fai Chau, Clarence John Dunnrowicz, Yan Chen, Chien Ping Lee
  • Patent number: 6159816
    Abstract: A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 12, 2000
    Assignee: TriQuint Semiconductor Texas, Inc.
    Inventors: Darrell G. Hill, Timothy S. Henderson, William U. Liu, Shou-Kong Fan, Hin-Fai Chau, Damian Costa, Ali Khatibzadeh
  • Patent number: 5552617
    Abstract: A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.
    Type: Grant
    Filed: August 16, 1995
    Date of Patent: September 3, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Darrell G. Hill, Timothy S. Henderson, William U. Liu, Shou-Kong Fan, Hin-Fai Chau, Damian Costa, Ali Khatibzadeh