Patents by Inventor Hin Hwa Goh
Hin Hwa Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150084213Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.Type: ApplicationFiled: September 25, 2013Publication date: March 26, 2015Applicant: STATS ChipPAC, Ltd.Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
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Patent number: 8916416Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.Type: GrantFiled: September 24, 2010Date of Patent: December 23, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Glenn Omandam, Yaojian Lin, Hin Hwa Goh
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Publication number: 20140246779Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.Type: ApplicationFiled: May 9, 2014Publication date: September 4, 2014Applicant: STATS ChipPAC, Ltd.Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
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Patent number: 8766426Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier.Type: GrantFiled: September 24, 2010Date of Patent: July 1, 2014Assignee: STATS ChipPac Ltd.Inventors: Hin Hwa Goh, Xusheng Bao, Yung Kuan Hsiao, Kang Chen, Rui Huang
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Patent number: 8759155Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.Type: GrantFiled: March 1, 2013Date of Patent: June 24, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
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Publication number: 20140110861Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.Type: ApplicationFiled: December 30, 2013Publication date: April 24, 2014Applicant: STATS ChipPAC, Ltd.Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
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Publication number: 20140077381Abstract: A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.Type: ApplicationFiled: November 14, 2013Publication date: March 20, 2014Applicant: STATS CHIPPAC, LTD.Inventors: Yaojian Lin, Jose A. Caparas, Kang Chen, Hin Hwa Goh
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Patent number: 8659162Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.Type: GrantFiled: September 26, 2011Date of Patent: February 25, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh, Kock Liang Heng, Jose A. Caparas
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Patent number: 8648470Abstract: A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.Type: GrantFiled: December 14, 2011Date of Patent: February 11, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Yaojian Lin, Jose Alvin Caparas, Kang Chen, Hin Hwa Goh
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Patent number: 8624364Abstract: An integrated circuit packaging system includes: a base integrated circuit package having a base integrated circuit on a base substrate thereof; a base barrier on the base substrate adjacent a base perimeter of the base substrate; a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier; and a cavity formed of the stack substrate, the base integrated circuit package, and the connector underfill, the cavity horizontally offset from the base barrier.Type: GrantFiled: February 26, 2010Date of Patent: January 7, 2014Assignee: Stats Chippac Ltd.Inventors: Seng Guan Chow, Hin Hwa Goh, Rui Huang, Heap Hoe Kuan
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Patent number: 8456002Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.Type: GrantFiled: December 21, 2011Date of Patent: June 4, 2013Assignee: STATS ChipPAC Ltd.Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
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Patent number: 8455991Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.Type: GrantFiled: September 24, 2010Date of Patent: June 4, 2013Assignee: STATS ChipPAC Ltd.Inventors: Yung Kuan Hsiao, Xusheng Bao, Kang Chen, Hin Hwa Goh, Rui Huang
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Publication number: 20130127039Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.Type: ApplicationFiled: September 24, 2010Publication date: May 23, 2013Applicant: STATS CHIPPAC, LTD.Inventors: Glenn Omandam, Yaojian Lin, Hin Hwa Goh
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Publication number: 20130113092Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.Type: ApplicationFiled: December 21, 2011Publication date: May 9, 2013Applicant: STATS CHIPPAC, LTD.Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
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Patent number: 8421212Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.Type: GrantFiled: September 22, 2010Date of Patent: April 16, 2013Assignee: Stats Chippac Ltd.Inventors: Kang Chen, Xusheng Bao, Rui Huang, Yung Kuan Hsiao, Hin Hwa Goh
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Publication number: 20130075922Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Inventors: Rui Huang, Xusheng Bao, Kang Chen, Yung Kuan Hsiao, Hin Hwa Goh
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Patent number: 8405230Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.Type: GrantFiled: January 14, 2011Date of Patent: March 26, 2013Assignee: STATS ChipPAC Ltd.Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Marie L. Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Rodriguez Dahilig
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Patent number: 8309451Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.Type: GrantFiled: July 30, 2008Date of Patent: November 13, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Stephen A. Murphy, Yaojian Lin, Heap Hoe Kuan, Pandi Chelvam Marimuthu, Hin Hwa Goh
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Patent number: 8304880Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; mounting a bottom integrated circuit over the bottom substrate; mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; connecting a top interconnect between the bottom substrate and the top substrate; and forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.Type: GrantFiled: September 14, 2010Date of Patent: November 6, 2012Assignee: Stats Chippac Ltd.Inventors: Seng Guan Chow, Hin Hwa Goh, Rui Huang, Heap Hoe Kuan
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Publication number: 20120261817Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.Type: ApplicationFiled: June 28, 2012Publication date: October 18, 2012Applicant: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Stephen A. Murphy, Yaojian Lin, Heap Hoe Kuan, Pandi Chelvam Marimuthu, Hin Hwa Goh