Patents by Inventor Hin Lum Lee

Hin Lum Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Probe system for QFP integrated circuit device test tooling
    Patent number: 11906550
    Abstract: An automated high speed test solution for Quad Flat Pack device packages that enables connectivity between test equipment and the integrated circuit under test is described. A test probe geometry that provides highly repeatable and reliable connections suitable for use with consumer grade QFP devices coupled with ease of maintenance is provided. In some embodiments, the probe tip ends are chisel-shaped. The probes can be slightly slanted with respect to a vertical axis of the probe retaining block.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 20, 2024
    Assignee: ESSAI, INC.
    Inventors: Nasser Barabi, Oksana Kryachek, Hin Lum Lee, Chee Wah Ho
  • PROBE SYSTEM FOR QFP INTEGRATED CIRCUIT DEVICE TEST TOOLING
    Publication number: 20220349918
    Abstract: An automated high speed test solution for Quad Flat Pack device packages that enables connectivity between test equipment and the integrated circuit under test is described. A test probe geometry that provides highly repeatable and reliable connections suitable for use with consumer grade QFP devices coupled with ease of maintenance is provided. In some embodiments, the probe tip ends are chisel-shaped. The probes can be slightly slanted with respect to a vertical axis of the probe retaining block.
    Type: Application
    Filed: October 29, 2021
    Publication date: November 3, 2022
    Inventors: Nasser Barabi, Oksana Kryachek, Hin Lum Lee, Chee Wah Ho
  • HYBRID SHIELDING SOCKETS WITH IMPEDANCE TUNING FOR INTEGRATED CIRCUIT DEVICE TEST TOOLING
    Publication number: 20220236302
    Abstract: High frequency operation of an integrated circuit test system is greatly extended by incorporation of a dedicated high frequency signal element that provides a circuit specific compensation network as part of the intermediation circuit board that enables connectivity between test equipment and the integrated circuit under test.
    Type: Application
    Filed: October 13, 2021
    Publication date: July 28, 2022
    Inventors: Nasser Barabi, Chee Wah Ho, Hin Lum Lee
  • SYSTEMS AND METHODS FOR HIGH SPEED TEST PROBING OF DENSELY PACKAGED SEMICONDUCTOR DEVICES
    Publication number: 20200379010
    Abstract: The present invention relates to systems and methods that enable a connection to be made to a high speed, packaged or unpackaged semiconductor device that preserves signal integrity using probes that exhibit the properties of a coaxial transmission line so as to provide an accurate representation of the environment in which the device under test will be used. The coaxial structure further reduces capacitive coupling between probes resulting in significantly improved crosstalk performance.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 3, 2020
    Inventors: Joven R. Tienzo, Hin Lum Lee, Joe Xiao, Chee Wah Ho, Nasser J. Barabi