Patents by Inventor Hina CHUJO

Hina CHUJO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thin film transistor array formed substrate, image display device substrate and manufacturing method of thin film transistor array formed substrate
    Patent number: 10629654
    Abstract: A thin film transistor array formed substrate including a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer formed in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 21, 2020
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Hina Chujo, Mamoru Ishizaki
  • THIN FILM TRANSISTOR ARRAY FORMED SUBSTRATE, IMAGE DISPLAY DEVICE SUBSTRATE AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY FORMED SUBSTRATE
    Publication number: 20180061892
    Abstract: A thin film transistor array formed substrate including a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer formed in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion.
    Type: Application
    Filed: October 23, 2017
    Publication date: March 1, 2018
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Hina CHUJO, Mamoru Ishizaki