Patents by Inventor Hinae Mizuno

Hinae Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9177974
    Abstract: An active matrix substrate includes a plurality of pixels arranged in a matrix, a plurality of capacitor lines (11b) extending in one of directions in which the pixels are aligned and in parallel to each other, a plurality of TFTs (5), one for each of the pixels, a protective film (16a) covering the TFTs (5), a plurality of pixel electrodes (18a) arranged in a matrix on the protective film (16a) and connected to the respective corresponding TFTs (5), and a plurality of auxiliary capacitors (6), one for each of the pixels. Each of the auxiliary capacitors (6) includes the corresponding capacitor line (11b), the corresponding pixel electrode (18a), and the protective film (16a) between the corresponding capacitor line (11b) and the corresponding pixel electrode (18a).
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto
  • Publication number: 20150287742
    Abstract: Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.
    Type: Application
    Filed: February 14, 2011
    Publication date: October 8, 2015
    Inventor: Hinae MIZUNO
  • Patent number: 9142573
    Abstract: Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 22, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Yamashita, Tokuo Yoshida, Yoshimasa Chikama, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto
  • Patent number: 9035295
    Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 19, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
  • Patent number: 9024311
    Abstract: The present invention provides a thin film transistor including an oxide semiconductor layer (4) for electrically connecting a signal electrode (6a) and a drain electrode (7a), the an oxide semiconductor layer being made from an oxide semiconductor; and a barrier layer (6b) made from at least one selected from the group consisting of Ti, Mo, W, Nb, Ta, Cr, nitrides thereof, and alloys thereof, the barrier layer (6b) being in touch with the signal electrode (6a) and the oxide semiconductor layer (4) and separating the signal electrode (6a) from the oxide semiconductor layer (4). Because of this configuration, the thin film transistor can form and maintain an ohmic contact between the first electrode and the channel layer, thereby being a thin film transistor with good properties.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: May 5, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Hara, Hirohiko Nishiki, Yoshimasa Chikama, Kazuo Nakagawa, Yoshifumi Ohta, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Miyajima, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Patent number: 8829513
    Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Patent number: 8698152
    Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiyuki Harumoto, Yoshifumi Ohta, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Okifumi Nakagawa, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
  • Patent number: 8685803
    Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: April 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
  • Patent number: 8592811
    Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: November 26, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiko Suzuki, Yoshimasa Chikama, Yoshifumi Ohta, Tokuo Yoshida, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
  • Publication number: 20130207114
    Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).
    Type: Application
    Filed: February 14, 2011
    Publication date: August 15, 2013
    Inventors: Masahiko Suzuki, Yoshimasa Chikama, Yuuji Mizuno, Hinae Mizuno, Yoshifumi Ohta, Tokuo Yoshida, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Tetsuya Yamashita
  • Publication number: 20130193430
    Abstract: The present invention provides an oxide semiconductor that realizes a TFT excellent in electric properties and process resistance, a TFT comprising a channel layer formed of the oxide semiconductor, and a display device equipped with the TFT. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, wherein the oxide semiconductor contains Ga (gallium), In (indium), Zn (zinc), and O (oxygen) as constituent atoms, and the oxide semiconductor has Zn atomic composition satisfying the equation of 0.01?Zn/(In+Zn)?0.22.
    Type: Application
    Filed: March 29, 2010
    Publication date: August 1, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ota, Hirohiko Nishiki, Yoshimasa Chikama, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130140552
    Abstract: A semiconductor device (100) according to the present invention includes: an oxide semiconductor layer (31) formed on an insulating layer (21), the oxide semiconductor layer (31) containing at least one element selected from the group consisting of In, Zn, and Sn; first and second sacrificial layers (41a) and (41b) formed, with an interspace from each other, on the oxide semiconductor layer (31); a second electrode (52a) formed in contact with an upper face of the first sacrificial layer (41a) and an upper face of the oxide semiconductor layer (31); and a third electrode (52b) formed in contact with an upper face of the second sacrificial layer (41b) and an upper face of the oxide semiconductor layer (31). The first and second sacrificial layers (41a) and (41b) contain an oxide having at least one element selected from the group consisting of Zn, Ga, Mg, Ca, and Sr.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 6, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshifumi Ohta, Takeshi Hara, Hinae Mizuno
  • Publication number: 20130134411
    Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).
    Type: Application
    Filed: April 5, 2011
    Publication date: May 30, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
  • Publication number: 20130105788
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor with excellent electric property and credibility, a thin film transistor having a channel layer formed of the oxide semiconductor, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, and includes Si, In, Zn, and O as constituent atoms.
    Type: Application
    Filed: May 6, 2010
    Publication date: May 2, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Okifumi Nakagawa, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Kazuo Nakagawa, Hinae Mizuno
  • Publication number: 20130099227
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor with excellent electric property, a thin film transistor having a channel layer formed of the oxide semiconductor, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor, and includes Al, In, Zn, and O as constituent atoms.
    Type: Application
    Filed: April 22, 2010
    Publication date: April 25, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Okifumi Nakagawa, Hirohiko Nishiki, Yoshimasa Chikama, Yoshifumi Ohta, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Kazuo Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130092923
    Abstract: An active matrix substrate includes a plurality of pixel electrodes (19a) arranged in a matrix, and a plurality of TFTs (5a) connected to the respective corresponding pixel electrodes (19a). Each TFT (5a) includes a gate electrode (11aa) provided on an insulating substrate (10a), a gate insulating layer (12) covering the gate electrode (11aa), an oxide semiconductor layer (13a) provided on the gate insulating layer (12) over the gate electrode (11aa) and having a channel region (C), and a source electrode (16aa) and a drain electrode (16b) provided on the oxide semiconductor layer (13a), overlapping the gate electrode (11aa) and facing each other with the channel region (C) being interposed between the source and drain electrodes. A protection insulating layer (17) made of a spin-on glass material is provided on the channel region (C) of the oxide semiconductor layer (13a).
    Type: Application
    Filed: January 12, 2011
    Publication date: April 18, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Hara, Hirohiko Nishiki, Yoshifumi Ohta, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130056741
    Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).
    Type: Application
    Filed: February 14, 2011
    Publication date: March 7, 2013
    Applicants: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiyuki Harumoto, Yoshifumi Ohta, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Okifumi Nakagawa, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
  • Publication number: 20130026462
    Abstract: A method for manufacturing a thin film transistor includes the step of forming a gate electrode (11aa) on an insulating substrate, the step of forming a gate insulating layer (12) to cover the gate electrode (11aa), and thereafter, forming an oxide semiconductor layer (13a) on the gate insulating layer (12), the step of forming a source electrode (16aa) and a drain electrode (16b) on the oxide semiconductor layer (13a) by dry etching, with a channel region (C) of the oxide semiconductor layer being exposed, and the step of supplying oxygen radicals to a channel region of the oxide semiconductor layer.
    Type: Application
    Filed: February 14, 2011
    Publication date: January 31, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Okifumi Nakagawa, Yoshifumi Ohta, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20130023086
    Abstract: An active matrix substrate includes a plurality of pixel electrodes (P) provided in a matrix, and a plurality of TFTs (5) connected to the pixel electrodes (P). Each of the TFTs (5) includes a gate electrode (11a) provided on an insulating substrate, a gate insulating film (12a) provided to cover the gate electrode (11a), an oxide semiconductor layer (13a) provided on the gate insulating film (12a) to overlap the gate electrode (11a), and a source electrode (17a) and a drain electrode (17b) facing each other and being connected to the oxide semiconductor layer (13a). A protective insulating film (14a) is provided between the oxide semiconductor layer (13a) and the source and drain electrodes (17a) and (17b) to cover the oxide semiconductor layer (13a).
    Type: Application
    Filed: August 23, 2010
    Publication date: January 24, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hiromitsu Katsui, Hirohiko Nishiki, Yoshifumi Ohta, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto, Hinae Mizuno
  • Publication number: 20120241750
    Abstract: A semiconductor device includes: a thin film transistor having a gate line (3a), a first insulating film (5), an island-shaped oxide semiconductor layer (7a), a second insulating film (9), a source line (13as), a drain electrode (13ad), and a passivation film; and a terminal portion having a first connecting portion (3c) made of the same conductive film as the gate line, a second connecting portion (13c) made of the same conductive film as the source line and the drain electrode, and a third connecting portion (19c) formed on the second connecting portion.
    Type: Application
    Filed: December 3, 2010
    Publication date: September 27, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimasa Chikama, Hirohiko Nishiki, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Takeshi Hara, Tetsuya Aita, Masahiko Suzuki, Michiko Takei, Okifumi Nakagawa, Yoshiyuki Harumoto