Abstract: A method to calibrate I/O cell current has been described. The method includes setting a global control value provided to the I/O cells. Then, for each I/O cell, the method includes comparing the logic voltage at the output pad of the I/O cell with a reference voltage, and sinking more current at the output pad by enabling additional driver bits associated with the I/O cell if the logic voltage is higher than the reference voltage, or sinking less current at the output pad by disabling additional driver bits associated with the I/O cell if the logic voltage is lower than the reference voltage.

Abstract: In some embodiments, the invention includes a system having first and second modules, the first module having a first group of chips and the second module having a second group of chips, and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first buffer on the first module and a second buffer on the second module, and a path including conductors in a first section that splits into a second section and third section, wherein the second section couples to the first buffer and the third section couples to the second buffer, and wherein impedances of the second and third sections are at least 50% greater than impedances of the first section.

Abstract: In some embodiments, the invention includes a module including a circuit board and first and second groups of conductors supported by the circuit board. A first group of chips each include on die terminations that are enabled. At least some of a second group of chips have on die terminations that are disabled. The first group of chips are coupled to conductors of the first group of conductors and the second group of chips are coupled to conductors of the second group of conductors, and wherein the second group of conductors have higher impedances than do the first group of conductors.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system includes a first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, and to on module terminations of the second module; and a second path of conductors extending from the circuit board to the second module connector, to the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module, and to on module terminations of the first module.

Abstract: In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.

Abstract: A local driver circuit to drive a logic voltage at an output pad includes an adder having K bits to add a K-bit control value to a local value, the adder producing a K-bit calibrated value. The circuit further includes K field-effect transistors (FETs), the drain of each FET being coupled to the output pad, and logic circuitry to perform a logical-AND function between a data input and the K-bit calibrated value. The logic circuitry providing a K-bit output with each of the K output bits being coupled to the gate of a corresponding one of the FETs. A comparator produces a correction value from a comparison of the logic voltage at the output pad and a reference voltage. A control unit sets a least significant bit (LSB) portion of the local value responsive to the correction value so as to make the logic voltage at the output pad in the reference voltage substantially equal.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system includes a first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, and to on module terminations of the second module; and a second path of conductors extending from the circuit board to the second module connector, to the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module, and to on module terminations of the first module.

Abstract: In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.

Abstract: In some embodiments, the invention includes a system having first and second modules, the first module having a first group of chips and the second module having a second group of chips, and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first buffer on the first module and a second buffer on the second module, and a path including conductors in a first section that splits into a second section and third section, wherein the second section couples to the first buffer and the third section couples to the second buffer, and wherein impedances of the second and third sections are at least 50% greater than impedances of the first section.

Abstract: A local driver circuit to drive a logic voltage at an output pad includes an adder having K bits to add a K-bit control value to a local value, the adder producing a K-bit calibrated value. The circuit further includes K field-effect transistors (FETs), the drain of each FET being coupled to the output pad, and logic circuitry to perform a logical-AND function between a data input and the K-bit calibrated value. The logic circuitry providing a K-bit output with each of the K output bits being coupled to the gate of a corresponding one of the FETs. A comparator produces a correction value from a comparison of the logic voltage at the output pad and a reference voltage. A control unit sets a least significant bit (LSB) portion of the local value responsive to the correction value so as to make the logic voltage at the output pad in the reference voltage substantially equal.