Patents by Inventor Hing (Thomas) Yan To

Hing (Thomas) Yan To has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Disparate clock domain synchronization
    Patent number: 8442075
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Quad rate transmitter equalization
    Patent number: 7991020
    Abstract: An integrated circuit includes current mode drivers that provide equalized outputs. A parallel-to-serial converter circuit receives data at less than one fourth the output data rate, and provides main data and equalization data at one fourth the output data rate to at least one four-to-one multiplexer. The main data and equalization data is multiplexed onto an output node at the output data rate.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Jun Cai, Matt Dayley
  • DISPARATE CLOCK DOMAIN SYNCHRONIZATION
    Publication number: 20110170584
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Disparate clock domain synchronization
    Patent number: 7936789
    Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 3, 2011
    Assignee: Intel Corporation
    Inventors: Hing (Thomas) Yan To, Gregory Lemos
  • Quad rate transmitter equalization
    Publication number: 20070230515
    Abstract: An integrated circuit provides equalized outputs. Main data and equalization data is produced at one fourth of the output data rate, and multiplexed onto an output node at the output data rate.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Hing (Thomas) Yan To, Jun Cai, Matt Dayley