Abstract: Optimizing timing margins across conditions is described. In one or more implementations, a computing system may include an interface circuitry configured to adjust a timing alignment of first and second signals between a central processing unit (CPU) of the system and a device coupled with the CPU and to measure and store one or more margins between the timing alignment and misalignments of the first and second signals. The interface circuitry may be configured to measure and store the timing margins at first and second conditions. The first and second conditions may be different voltages, temperatures, etc. The system may be configured to force the first and/or second condition. The system may be configured to calculate a coefficient from differences in between the margins and between the first and second conditions.

Abstract: In-system electrical connectivity detection. In one or more implementations, a computing device includes a transmitter and a receiver in a package, the transmitter to transmit a signal to a separate device, the receiver to receive and measure a reflection of the transmitted signal, and the measured reflection for characterizing (e.g., testing or detecting) an electrical connection between the computing and separate devices. The computing device may characterize (e.g., detect a discontinuity in) the electrical connection by comparing a magnitude of the transmitted signal with a magnitude of the measured reflection. The computing device may be coupled with the separate device by multiple electrical connections, and the multiple electrical connections may be tested by corresponding transmitters and receivers.

Abstract: A compression-defined broaching mount for compression-attached memory module (CAMM) includes a plurality of pins configured to retain a plurality of circuit boards in a compressed position. The pins may include a snap-pin, a push-pin, and/or a spring-loaded pin. The pin is removable. The CAMM may include a flat washer and/or a counter-sunk washer configured to receive the pin. The counter-sunk washer may have an opening to a chamber therein, where an inner surface of the chamber has a channel to receive a locking member of the pin. The CAMM may include a compressible material to exert a force when the pin is in a locked position. The compressible material may include an O-ring, a gasket, and/or a film. The CAMM may include a visual compression indicator.

Abstract: A semiconductor device comprises a printed circuit board (PCB), a plurality of vias, and a communication buss. The PCB comprises a plurality of layers. The first layer of the plurality of layers is configured to receive a first integrated circuit (IC) device and a second IC device. The plurality of vias is disposed within the plurality of layers. A first via of the plurality of vias is configured to be connected to the first IC device, and a second via of the plurality of vias is configured to be connected to the second IC device. The communication bus comprises a first trace connected to the first via. The communication device further comprises a second trace disposed on a third layer of the plurality of layers and connected to the first via. The first trace is disposed on a layer of the plurality of layers other than the second layer.

Abstract: Error alert encoding for improved error mitigation is described. In one or more implementations, a system includes a processor configured to receive an encoded signal indicating a type of an error detected in a memory, and output one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. In one or more implementations, a memory system includes a memory and a buffer. The buffer is configured to output an encoded signal indicating a type of an error detected in the memory.

Abstract: A semiconductor device comprises a printed circuit board (PCB), a plurality of vias, and a communication buss. The PCB comprises a plurality of layers. The first layer of the plurality of layers is configured to receive a first integrated circuit (IC) device and a second IC device. The plurality of vias is disposed within the plurality of layers. A first via of the plurality of vias is configured to be connected to the first IC device, and a second via of the plurality of vias is configured to be connected to the second IC device. The communication bus comprises a first trace connected to the first via. The communication device further comprises a second trace disposed on a third layer of the plurality of layers and connected to the first via. The first trace is disposed on a layer of the plurality of layers other than the second layer.

Abstract: Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.

Abstract: Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.

Abstract: A circuit for controlling the bias current in a differential amplifier is disclosed. A differential amplifier comprising complementary differential input transistor pairs includes variable bias current sources to provide bias currents to the differential input pairs. The variable bias current sources are coupled to an input current control unit that includes one or more programmable switches to vary the amount of bias current supplied to the differential input pairs. The slew rate, differential gain, and common mode input range of the differential amplifier may be varied by adjusting the bias currents to the differential input pairs. A cascode circuit is coupled between the differential input pairs and their respective load circuits to extend the common mode input range to the supply voltage rail values.