Abstract: In some aspects, a method may include receiving, at a memory interface of a device configured as memory, using a memory access protocol, a request to make a region of memory allocatable; and processing the request to make the region of memory allocatable. Processing the request may include making allocatable at least a portion of storage media of the device corresponding to the region of memory and/or assigning a value to at least a portion of the storage media corresponding to the region of memory. The device may be configured to track allocated addresses on the device, and the method may further include modifying at least one circuit to make addresses allocatable corresponding to the region of memory. The method may further include modifying the device to indicate that the region of memory is free and adding the region of memory to a list of allocatable memory locations.

Abstract: A method may include determining that data is related to an operation of an operating system; determining a score for the data; and writing the data to memory media based on the score. The data may include at least one page table. The at least one page table may include one or more entries; the one or more entries corresponds to data accessed above a threshold; and the method may further include writing data corresponding to the data accessed above a threshold from storage media to the memory media and/or storing data corresponding to the data accessed above a threshold in the memory media. The one or more entries may correspond to data accessed below a threshold; and the method may further include modifying data corresponding to the data accessed below a threshold from the memory media to storage media.

Abstract: A device is disclosed. The device may include a memory to store a data, a controller to manage the memory, and a storage media to store a copy of the data. A module may support page swapping with a memory associated with a processor.

Abstract: A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

Abstract: Systems and methods for demand-based storage are disclosed. A first storage device is coupled to a first computing device over a first link. The first storage device includes a storage medium and a processing circuit connected to the storage medium. The processing circuit may be configured to: receive a first request for a first storage capacity; transmit a second request for allocating at least a portion of the first storage capacity on a second storage device configured to communicate with the first storage device over a second link; receive a first storage command from the first computing device; generate a second storage command based on the first storage command; and transmit the second storage command to the second storage device for execution of the second storage command by the second storage device.

Abstract: An interface for enabling a computer device to utilize data property-based data placement inside a nonvolatile memory device comprises: executing a software component at an operating system level in the computer device that monitors update statistics of all data item modifications into the nonvolatile memory device, including one or more of update frequencies for each data item, accumulated update and delete frequencies specific to each file type, and an origin of the data item; storing the update statistics of each of the data items and each of the data item types in a database; and intercepting all operations, including create, write, and update, of performed by applications to all the data items, and automatically assigning a data property identifier to each of the data items based on current update statistics in the database, such that the data items and assigned data property identifiers are transmitted over a memory channel.

Abstract: A system and method for satisfying Quality of Service (QoS) attributes for a stream using a storage device with multi-stream capability is described. The storage device may include memory to store data. A host interface may receive requests, some of which may be associated with a stream. A host interface layer may schedule the requests in a manner that may satisfy the QoS attribute for the stream.

Abstract: A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

Abstract: An interface for enabling a computer device to utilize data property-based data placement inside a nonvolatile memory device comprises: executing a software component at an operating system level in the computer device that monitors update statistics of all data item modifications into the nonvolatile memory device, including one or more of update frequencies for each data item, accumulated update and delete frequencies specific to each file type, and an origin of the data item; storing the update statistics of each of the data items and each of the data item types in a database; and intercepting all operations, including create, write, and update, of performed by applications to all the data items, and automatically assigning a data property identifier to each of the data items based on current update statistics in the database, such that the data items and assigned data property identifiers are transmitted over a memory channel to the non-volatile memory device.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

Abstract: A device is disclosed. A storage device may include storage for a data and a controller to manage access to the storage. A network interface device may send the data across a network. A host interface may receive a request for the storage device or the network interface device.

Abstract: A system and method for satisfying Quality of Service (QoS) attributes for a stream using a storage device with multi-stream capability is described. The storage device may include memory to store data. A host interface may receive requests, some of which may be associated with a stream. A host interface layer may schedule the requests in a manner that may satisfy the QoS attribute for the stream.

Abstract: A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

Abstract: Example embodiments are described for data property-based data placement inside a nonvolatile memory device performed by a storage controller of the nonvolatile memory device.

Abstract: An interface for enabling a computer device to utilize data property-based data placement inside a nonvolatile memory device comprises: executing a software component at an operating system level in the computer device that monitors update statistics of all data item modifications into the nonvolatile memory device, including one or more of update frequencies for each data item, accumulated update and delete frequencies specific to each file type, and an origin of the data item; storing the update statistics of each of the data items and each of the data item types in a database; and intercepting all operations, including create, write, and update, of performed by applications to all the data items, and automatically assigning a data property identifier to each of the data items based on current update statistics in the database, such that the data items and assigned data property identifiers are transmitted over a memory channel to the non-volatile memory device.

Abstract: A device is described. The device may include a connector to connect the device to a component. The device may also include a computational storage unit. A receiver may receive a discovery request from a discovery service, and a transmitter may transmit a discovery response to the discovery service, the discovery response including information about the computational storage unit.

Abstract: An interface for enabling a computer device to utilize data property-based data placement inside a nonvolatile memory device comprises: executing a software component at an operating system level in the computer device that monitors update statistics of all data item modifications into the nonvolatile memory device, including one or more of update frequencies for each data item, accumulated update and delete frequencies specific to each file type, and an origin of the data item; storing the update statistics of each of the data items and each of the data item types in a database; and intercepting all operations, including create, write, and update, of performed by applications to all the data items, and automatically assigning a data property identifier to each of the data items based on current update statistics in the database, such that the data items and assigned data property identifiers are transmitted over a memory channel to the non-volatile memory device.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a flash memory to store data and support for a number of device streams. The SSD may also include an SSD controller to manage reading data from and writing data to the flash memory. The SSD may also include a host interface logic, which may include a receiver to receive the commands associated with software streams from a host, a timer to time a window, a statistics collector to determine values for at least one criterion for the software streams from the commands, a ranker to rank the software streams according to the values, and a mapper to establish a mapping between the software streams and device streams.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.